Optimum Implementation of a high-Throughput QC-LDPC Decoder Based on Layered Decoding

This paper presents a high throughput decoder for QC-LDPC codes. In the proposed architecture, based on layered min sum decoding, a novel technique for simultaneous process of rows and columns is presented, that reduced the number of clock cycles in per iteration and as result the throughput is increasing. The proposed decoder is presented for any code length (576:96:2304), in code rate 1/2 and 7-bit quantization in 802.16e standard. Based on proposed decoder, QC-LDPC decoder is synthesized for code length 2304, on 130 nm CMOS technology by Synopsys Design Compiler. The obtained results in the operating frequency of 100 MHz and 10 iterations show that the maximum throughput is 198 Mb/s and total power consumption of 156.39mW and chip area of 5.09 mm2.