Enhanced Current Comparison Based Domino for Design of Power Wide Fan - In Gates

In this paper, a new domino circuit is proposed to reduce power consumption of wide fan-in gates without considerable speed degradation. In the proposed domino circuit technique, current of the pull-down network is compared with a reference current to generate the proper output voltage. In this way, voltage swing of the pull-down network can be decreased to reduce power consumption. Moreover, a transistor in diode configuration is employed in series with the pull-down network to decrease the sub-threshold leakage current and increase the noise immunity. Simulation of wide fan-in OR gates are performed using HSPICE simulator in a 90nm CMOS technology model. Simulation results demonstrate 39% power reduction and 2.1× noise-immunity improvement at the same delay compared to the standard domino circuit for 64-bit OR gates.