Thermally aware circuit modeling and performance analysis of single-walled carbon nanotube bundle as VLSI interconnects

Temperature dependent, delay, power dissipation and power delay product (PDP), in single walled carbon nanotube (SWCNT) bundle interconnect have been analyzed. Thermally aware circuit model for metallic SWCNT bundle is presented. The results are compared with those of currently used copper interconnects at 22nm technology node. It is seen that delay, power dissipation and PDP of SWCNT bundle interconnect increase with rise in temperature from 300K to 450K at different interconnect lengths from 100µm to 1000µm . It is also observed that, with rise in temperature, SWCNT bundle has a lower delay than that of copper for all interconnect lengths whereas reverse is true for power dissipation. In addition, with rise in temperature from 300K to 450K, for interconnect lengths at 100µm and 400µm SWCNT bundle has lower PDP compared to copper interconnects whereas reverse is true for interconnect lengths at 700µm and 1000µm. Moreover, relative average improvement in delay, power and PDP using thermally aware model in comparison with temperature independent model is estimated. Based on simulation results, the thermally aware model of SWCNT bundle achieved improvement in delay, power and PDP estimation accuracy of about 22.44%, 7.59% and 31.96% on average.