8T SRAM Cell Design in Sub-Threshold Region with Differential Write Ability and Single Ended Read with Bit Interleaving Capability

In this paper, a 8T SRAM cell in sub-threshold region is presented which in addition to read and write operation improvements, reduces power consumption significantly. The proposed cell carries out write operation differentially and has a single ended read operation. In this design, using an appropriate combination of techniques, leads to improvements the cell performance. These methods include weakening feedback in the write mode, applying the boosted word line, eliminating one of the driver transistors and isolating storage node from access transistor by a buffer. The simulation results at 32 nm PTM technology and VDD 0. 3 V show the proposed cell improves read and write power consumption 93%and 80%, respectively compared with 6T cell. Moreover, the proposed cell has lower power consumption and stronger write mode compared with other bit interleaving cells. Furthermore, the proposed cell has a desired performance in the read mode.