Design of a Novel Ultra-Low Power SRAM Cell with Improved Read SNM

Today static memories are one of important parts of digital circuits and due to appropriate speed and power are used to build embedded memories which are the SOC vital parts. Static memories are also used to create caches. With increased demand for battery driven applications, methods for reduce power consumption in the memory blocks receive special attention. Static memory cells are in hold mode most of the times, in addition when static memory size becomes large, static power will become significant and the most of power consumption will belong to it. Thus reduce static power becomes a priority. In this paper, a new low power SRAM with ability to separate read and write path is presented. The static power of proposed structure is reduced 78. 21% than the conventional six-transistor cell, and read static noise margin is enhanced 202. 59% rather than the conventional six-transistor cell. In order to evaluate the performance of the proposed cell and comparing the results, simulations are done in TSMC 130nm CMOS technology and the supply voltage of 1. 2 V.