Linearity and Stability Improvement of the Ramp Generator with Low Power Consumption for Single-Slope ADCs

Linearity and power dissipation of ramp signals are the main key aspects for many applications such as single-slope ADCs. This paper presents a low power ramp generator with linearity improvement and a negative feedback for compensation of the variations in process, voltage, and temperature (PVT). In addition an approach for offset cancelation of ramp generator is presented. Derived equations of the proposed ramp generator circuit show the linearity improvement and PVT compensation of the output ramp, with proper choosing of device sizes. In addition, for proving of linearity enhancement, the circuit design and simulations were done in TSMC 0.18-μm technology with Cadence software. Corners analysis and Monte Carlo Simulation results show that linearity of the circuit improved more than 1-bit and 2-bit, respectively. While power dissipation of the circuit and total layout core area are not increased so much in comparison with conventional circuit.