Lowering Power Consumption and Improving Resistance Against Power Analysis Attack of an Adder with Graphene-Based Emerging Technology

In this paper, for the first time, the role of graphene-based emerging technology has been investigated in digital adder circuits. The aims are to decrease power consumption and enhance security against power analysis attack. Static and current mode logic (CML) styles are employed to design one, four, and eight-bit adders in silicon and graphene technologies. In simulations, a SPICE-compatible model for graphene transistors and a PTM model for silicon FINFET transistors are used. Results reveal that the graphene-based static adders show the least power consumption. For an 8-bit adder, power overshoots and standard deviation from power traces confirm that a graphene-based CML (G-CML) adder is the most robust scheme against power analysis attack among the static and CML designs. Eventually, a new hybrid approach is proposed by providing a circuit in which security is enhanced by creating an irregularity in the power trace and this makes the data detection more difficult. Accordingly, an adder based on the proposed approach yield higher security with a different pattern of a power trace and also contains lower power consumption than pure CML-based adders.