Design and Simulation of 4 Transistors and 2 Memristors Memory with the Least Power and Power-Delay Product

Memristor, as a fundamental element of SRAM and DRAM memories, can effectively reduce startup time and power consumption of the circuits. Non-volatility, high density of the final circuit, and reduction of power delay product (PDP) are some of the significant facts of memristor circuits, which has led to the suggestion of a memory cell including and four transistors and two memristors (4T2M) in this paper. In order to simulate the proposed memory cell, the length of memristors has been selected 10 nm, and their on/off state resistors have been selected 250 Ω and 10 KΩ respectively. In addition, the proposed memory cell MOS transistors are simulated by the 32 nm CMOS PTM model. Simulation in the HSPICE software with 1V supply voltage and comparison with two conventional six-transistor (6T) and two transistors-two memory (2T2M) cells show that the use of memristors has made the proposed memory cell and 2T2M cell non-volatile. Moreover, the power consumption of the proposed circuit has decreased by 99.8% and 57.2%, compared to the previous two circuits respectively, and the power average delay product has also improved by 99.4% and 26.7%, respectively; however, the writing delay of this cell and 2T2M cell increased by 400% and 218% compared to 6T cell, respectively.