Formal Verification of System-Level Power Management Architecture in Modern Processors

As the complexity of low-power designs grows, more efficient and automated tools are needed to functionally verify them. Simultaneous verification of both the design functionality and the consistency of power management controllers with the low-level power intent is a big challenge. This paper presents a method which attempts to resolve such a problem for complicated processors with tens of power domains. In order to ensure that the functionality of the processor after inserting power management controllers does not change, an efficient equivalence checking is performed between the low-power implementation model and its specification model. However, this kind of verification is not sufficient due to non-functional behavior of system-level power management strategies. Therefore, the proposed method checks the consistency between PMU and UPF by high-level power rules which are extracted from UPF. The experimental results show that the proposed method helps the designers not only to create a correct high-level power management controller but also to identify the low-power functional bugs in their designs.