The Circuit Design of the Receiving Part of the portable Electroencephalogram System

In recent years, many electroencephalogram (EEG) devices have become portable and wireless. Given the requirements for mobility, EEG instruments need to be smaller, lighter, and power-efficient with reduced noise and offset. An EEG signal is very weak and its amplitude ranging is from 20 to 200 µV and its frequency ranges from 0.1 to 100 Hz. Besides, the skin-electrode interface creates a large DC offset voltage which can be in the order of ±300 mV. These two challenges can disturb the main signal and reduce the detection accuracy. At the input of amplification section of many EEG circuits, the chopping technique has been applied to convert DC input signals into AC signals. The main transconductance amplifier as EEG instrumentation amplifier (IA) in most of the previous works is the folded cascode amplifier. In this paper, we proposed a circuit which designed in 0.18 CMOS technology and its amplifier is a two-stage fully recycling chopper stabilized folded cascode amplifier that operates at low supply voltage and its input-referred noise is decreased by enhancing transconductance while it has a large slew rate, a high DC gain and an improved gain bandwidth. These features significantly decrease the noise and offset without a considerable increase in the power required by the circuit. In the post-layout simulation the amplifier achieves a midband gain of 60 dB and a -3dB bandwidth in the range of 0.1-210 Hz. the chip area with pads is 512×512 μm2. The adjustable LPF has a 100 Hz cut-off frequency.