A Defect Tolerant Design for 5-Input Majority Gate in Quantum-dot Cellular Automata

Quantum-dot cellular automaton is a new technology for implementation of logic gates and digital circuits at nanoscale. By reducing size of the components, sensitivity of circuit increases and quantum circuits become more vulnerable to adverse environmental factors. Due to the importance of designing fault tolerant circuits, this paper presents a five-input majority gate with fault tolerance characteristic in quantum cellular automata technology. All possible faults which may occur during the process of placing cells in specific locations on the surface including displacement, deletion, rotation, and extra cell are evaluated.  In the first step, all the four types of faults are applied to the gate and the next step is to evaluate the accuracy of the gate performance with the QCADesigner simulator. In order to find such a majority gate, different methods, including the method of adding cells (the injection of redundancy to the gate) and the specific arrangement of cells are utilized. The latter method is being used more, hence, low overhead is added to the design.  The results confirm the superiority of the proposed gate over the other previously offered designs.