SA-based Approach to Implement Digital Systems on 3D Integrated Circuits

The 3D integrated circuit is emerged as a promising solution to integrate very large-scale circuits on electronics chips. In such chips, several layers of silicon substrates are stacked which are separated by insulator interfaces. Interconnection between two layers is realized using Through Silicon Via (TSV). Fabrication of TSVs is challenging due to their large size and complex process. Consequently, the number of TSVs should be minimized in the circuit’s implementation. The 3D implementation consists of three main steps: Partitioning, Placement, and Routing. In this paper, the first two steps are accomplished using the Simulated Annealing-based optimization approach wherein minimization of the number of TSVs and total wire length are considered the main objectives. In this paper, an improved version of the pathfinder method has been developed which would efficiently generate the necessary interconnections among circuit modules. The results of simulations on MCNC benchmark circuits show that the proposed method outperforms the previous state-of-the-art methods in all aspects. In comparison with FSA, the number of TSVs is reduced by 6.15%, and the algorithm’s runtime is decreased by 27.79%. Moreover, in comparison with the hMETIS method, the number of TSVs is reduced by 9.78%, and the algorithm’s runtime is decreased by 31.73% .