Design and Synthesis of High Speed Low Power Signed Digit Adders

Signed digit (SD) number systems provide the possibility of constant-time addition, where inter-digit carry propagation is eliminated. Such carry-free addition is primarily a three-step process; adding the equally weighted SDs to form the primary sum digits, decomposing the latter to interim sum digits and transfer digits, which commonly belong to {–1, 0, 1}, and finally adding the transfers to the corresponding (i.e., with the same weight) interim sum digits. All the final sum digits are therefore obtained in parallel. The special case of radix-2h maximally redundant SD number systems is more attractive due to maximum symmetric range (i.e., [–2h+1, 2h–1]) with only one redundancy bit per SD, and the possibility of more efficient carry-free addition. The previous relevant works use three parallel adders that compute sum and sum±1, where some speed-up is gained at the cost of more area and power. In this paper, we propose an alternative nonspeculative addition scheme that uses carry-save encoding for representation of the primary sum and interim sum digits and computes the transfer digits via a fast combinational logic. The simulation and synthesis of the proposed adder, based on 0.13 μm CMOS technology, shows advantages in terms of speed, power and area.