A Low Voltage Low Power CMOS Implementation of Second Generation Orderly Current Buffer

In this paper, a novel low voltage low power current buffer was presented. The proposed structure was implemented in CMOS technology and is the second generation of OCB (orderly current buffer) called OCBII. This generation is arranged in single input-single output configuration and has modular structure. It is theoretically analyzed and the formulae of its most important parameters are derived. Pre and Post-layout plus Monte Carlo simulations were performed under ±0.75 V by Cadence using TSMC 0.18 µm CMOS technology parameters up to 3rd order. The proposed structure could expand and act as a dual output buffer in which the second output shows extremely high impedance because of its cascode configuration. The results prove that OCBII makes it possible to achieve very low values of input impedance under low supply voltages and low power dissipation. The most important parameters of 1st, 2nd and 3rd orders, i.e. input impedance (Rin), -3 dB bandwidth (BW), power dissipation (Pd) and output impedance (Ro) were found respectively in Pre-layout plus Monte Carlo results as: 1st order: Rin (52.4 Ω), BW (733.7 MHz), Pd (225.6 µW), Ro (105.6 kΩ) 2nd order: Rin (3.8 Ω), BW (576.4 MHz), Pd (307 µW), Ro (106.4 kΩ) 3rd order: Rin (0.34 Ω), BW (566.9 MHz), Pd (535.6 µW), Ro (118.2 kΩ) And in Post-layout plus Monte Carlo results as: 1st order: Rin (59.9 Ω), BW (609.6 MHz), Pd (212.4 µW), Ro (106.9 kΩ) 2nd order: Rin (11.3 Ω), BW (529.3 MHz), Pd (389.9 µW), Ro (109.8 kΩ) 3rd order: Rin (5.8 Ω), BW (526.5 MHz), Pd (514.5 µW), Ro (125.5 kΩ) Corner cases simulation results are also provided indicating well PVT insensitivity advantage of the block.