عبدالرضا نبوی

Human activities everyday release a huge amount of domestic, industrial and agricultural waste into water bodies and continuously change the ecosystem conditions in the world. Considering the harmful effects of these pollutants entering water resources, study about pollution transfer in streams and predicting the pollutant concentration at downstream points seem to be important. For this purpose, the well-known classical advection-dispersion equation (ADE) was presented as the first attempt for describing mass transfer and energy transfer in physical systems. This equation is useful for channels with relatively prismatic and uniform cross-sections. Experimental studies carried out in rivers show that ADE is no longer applicable for natural streams, especially mountain pool and riffle streams because of their irregular cross-sections. Afterward, some more accurate models, referred dead zone models or transient storage models, were suggested by several researchers for predicting solute concentration in natural rivers and calibrated using tracer approach. Such models cause more realistic concentration-time distributions which have lower picks and longer residence time. Solving such models, for which in most cases the analytical solution doesn’t exist, needs numerical methods –methods which usually deal with complexity and is time-consuming. In this study, we have applied Network Simulation Method (NSM) –a powerful and efficient computational method for simulating systems governed by differential equations based on the electric circuit concepts and the analogy between the governing differential equations of hydrodynamic and electrical phenomena– which according to the previous studies simulates desirably the transport of mass in natural streams, to solve two transient storage models. The method consists of two phases of designing and simulating. In designing phase, the system of differential equations corresponding to the prototype must be discretized spatially over the studied domain and then, for each term of the discretized equations the equivalent electrical devices are chosen. These electrical elements are connected based on the algebraic sign of the terms to satisfy Kirchhoff’s current low. Regarding the mathematical models, in most studies, electric potential and electric current are equivalent to the value of the unknown variable and its flux, respectively. The last step of designing the electro-analogical model is the implementation of initial conditions and boundary conditions of unknown variables using appropriate dependent and/or independent, voltage and/or current sources. Simulating this equivalent electrical network is performed through an appropriate electrical-computational circuit code, such as PSpice code. PSpice, which is a powerful circuit analysis software, uses the Newton-Raphson iterative algorithm to solve this set of nonlinear equations and performing the transient analysis. In this paper, NSM is firstly verified by simulating a transient storage transport model developed by Bencala and Walters (1983) for unsteady conservative solute transfer in pool and riffle streams. This model includes two equations for solute concentration in the main channel and in the storage zone and involves one storage zone. The analytical solution for this model has been presented in Laplace domain by Kazezyılmaz-Alhan (2008) considering a hypothetical channel with a constant cross-sectional area, flow velocity, and dispersion coefficient and for two types of upstream boundary conditions including a continuous injection and a pulsating solute injection. The results of this verification were desirable. Then, the accuracy and efficiency of NSM were compared with Finite Volume Method (FVM) –a widely used numerical method in computational fluid dynamics- through simulating an unsteady reactive solute transport using a nested two-storage zone transport model developed by Kerr et al. (2013). This model consists of three equations and involves two storage zones including the surface and hyporheic storage zones interacting together. The results of simulating a hypothetical solute transport problem with this nested model indicate a good match between these two methods with near-zero error indices. The computational time needed for NSM and FVM were 117 seconds and 505 seconds, respectively. So, NSM is much faster. Furthermore, the implementation of boundary conditions in NSM is direct, easier and more flexible. Therefore, NSM is proposed as a precise and efficient alternative for numerical methods in solving one-dimensional coupled differential equations of unsteady transport, simultaneously and providing benchmarks without complex mathematical calculations. Because of its analogical based concept, it can be used as a predicting and monitoring tool for transport phenomena instead of using troublesome physical hydraulic models to perform the water quality studies with less time, low expense and higher accuracy. Hence, in critical conditions, including a sudden spill of a high-hazardous contaminant in a specified point of the river or increasing the concentration of a chemical element to its maximum level, the monitoring and controlling measures at different parts of the river can be carried out with an acceptable accuracy and speed to improve the water quality.

In this paper, a Low Noise Variable Gain Amplifier in Ka-frequency band is designed. This amplifier is digitally controlled by using switching transistors which change the gain with an accuracy of 5-bit resolution (32 steps). The output phase shift should be minimized within a Dynamic Range of 15 dB. The proposed structure includes a Low Noise Amplifier and a Variable Gain Amplifier, with common-source structure and degenerative inductor. In the proposed structure, the main gain is achieved by LNA and the switching control bits are used in two stages of the VGA. Simulation illustrates a Noise Figure of 5. 6 dB; bandwidth of 5. 34 GHz; S11, S22 less than -14 dB and Dynamic Range of 15 dB. By using a “compensating inductor” in the source of switching transistors, the amount of phase shift was reduced, such that within the bandwidth of 1. 5 GHz it is less than 5 degrees. The post-layout simulation results, show a Dynamic Range of 18. 7 dB; a bandwidth of 2. 5 GHz; Noise Figure of 6. 4 dB and return losses less than -10 dB. In addition to it, In EM analysis, all inductors and major RF paths are evaluated by “Sonnet” software.

Reducing emissions and fuel consumption have always been a major concern of engine manufacturers. In recent years, strict emission laws and fast reduction of fossil fuel resources have increased this concern. Main purpose of this work is to optimize D87 diesel engine with consideration of parameters such as amount of soot emission, BSFC and maximum pressure of combustion chamber. Effect of pre injection on engine performance has been investigated experimentally. Test is done for four different load points in constant maximum speed which at each load point 3 up to 7 percent of total fuel mass is considered in pilot injection. Results show that BSFC is decreased with increasing of pre injected fuel. From the other side soot emission and maximum pressure of combustion chamber are increased by increasing of pre injected fuel, but both of them are still in an acceptable level so the optimum point is selected based on the minimum BSFC. In all cases minimum BSFC is reached by considering 7 percent of total fuel mass in pre injection which the minimum amount of BSFC is about 194 g/kW.h at 1000 kW.

This paper presents envelope shaping and linearization techniques for envelope-elimination-and-restoration (EER) power amplifiers in wideband applications. Although the EER technique can enhance the efficiency of the power amplifier, its use in the OFDM-based systems with stringent mask and EVM requirements needs additional considerations, especially for wideband signals. To satisfy the required spectral mask and EVM of the transmitter, two digital pre-distortion algorithms are implemented and compared for linearization of the EER system. To increase the output power and efficiency, envelope clipping technique is proposed for the EER transmitter. The imposed nonlinearity caused by the clipping can be reduced by the pre-distortion. Further, time delay mismatch between amplitude and phase paths is investigated and a solution is proposed for its alleviation. For accurate and realistic results, these techniques are tested under interlock operation of digital, analog, and RF segments of the EER system for 802.16e WiMAX signal. The co-simulation results show that the proposed techniques can enhance the efficiency and output power while satisfying the required linearity of the transmitter.

In this paper, a very low phase noise oscillator is proposed. Phase noise of the proposed VCO is lower than the lowest attainable phase noise of the conventional topologies. In the proposed circuit a fourth-order tank is employed, also the the current waveform injected the tank is class-C which provide the best DC to RF efficiency. Phase noise of the proposed oscillator has been theoretically investigated and closed-form formulae have been derived that shows the amount of phase noise improvement achieved by using the proposed circuit for different tank elements. 6 dB phase noise improvement in current-limited regime is achieved by using the proposed technique with same tank elements in comparison with the conventional topologies. In order to verify the derived formulae, the results of the calculations have been compared against simulation results. Their match are excellent.

In this paper, according to the size of the transistors and the feedback gain of the oscillator, a design point in which the gain of the active core of the oscillator is maximum, is derived. In order to realize the feedback gain, we utilize a transformer. This transformer is employed in such a way that it could be able to provide the feedback gain for the oscillator and also eliminate the large portion of parasitic capacitance, simultaneously. By using this technique, the phase noise at 1MHz offset and the tuning range in comparison with the general transformer oscillator is improved by 5dB and 70% respectively. Furthermore, we show that with linearization of the oscillator in millimeter-wave frequencies, phase noise of the oscillator can also be reduced even more. Regarding this criteria we linearize the oscillator as much as possible. Post-simulation results show that the circuit designed in 0.18-μm CMOS technology, consumes 43mW while showing -89dBc/Hz phase noise at 1MHz offset with 1.9GHz tuning range around 57GHz.

In this paper a Time-Amplifier, one of the most significant blocks of the time domain signal processing modules will be designed and simulated. Time domain signal processing is one of the most forerunner alternatives for the amplitude domain signal processing specially in nowadays nanotechnology devices. The main core of a time mode processor is a Time-to-Digital Converter (TDC). Increasing the resolution of the TDC, the processing of the signal is performed with higher quality. One of the most challenging efforts is the processing of two signals with very small time difference between their edges. Recently, some new techniques are proposed to overcome this significant problem. One of these techniques is amplifying the time difference, before employing it into the time mode signal processor or a TDC. Regarding this bottleneck, in this paper a high resolution, high gain, highly linear time amplifier (TAMP) with a large dynamic range (DR) is designed. The pre-detector of this TAMP, is a novel digital Pulse-to-Edge Converter (PEC) which also can operate in high frequencies. This TAMP is utilized in a proposed TDC in order to give one important utility of the circuit. The proposed topology is designed in a 0.18μm CMOS process and simulated via ADS2009 and Cadence® (Spectre RF). The simulation results illustrates the total power consumption is 1.7 mW, occupied area of the chip is below 0.35 mm2, time resolution is 5 psec, gain of the TAMP is approximately near to 200 s/s and the total linear DR of the TAMP is almost 350 psec.

In this paper a 5th-Order single-loop Sigma-Delta Modulator with low distortion structure is presented. This structure, which uses integrator and IIR filter concurrently, has relatively less feedforward paths and modulator coefficients. Thus, its sensitivity to coefficient mismatching is reduced. To lower the power consumption of the modulator, the 2-order IIR filter block is implemented by single OTA, and a passive adder is used to realize input quantizer adder. Simulation results show that this structure can achieve 15-bit of resolution and 6 MHz input signal bandwidth, with 1.2 V supply voltage using a 0.13 µm CMOS technology. Power consumption of modulator is 53 mW. Comparing with other structures, the proposed modulator has higher performance because of increasing the DR and input bandwidth of modulator without extra increasing the power consumption.

This paper describes the design of hybrid wave-pipeline architecture for implementation of real time morphological dilation. With minor changes to this architecture, it can be utilized for erosion, closing, and opening operators. The new architecture results in higher speed, less hardware complexity, and lower area and power dissipation compared to conventional pipeline implementation. In addition, it is faster than the wave-pipeline structure, without the difficulty of balancing the delay of long signal paths. Using the new architecture, three ASIC chips in 0.18µm CMOS are designed for binary image processing through Verilog. These chips dilate a 1024×1024 image by a 21×21 structuring element in 256.58μ s. The maximum frequency of the operations is 5.882 GHz, 5 GHz, and 4.167 GHz. For the power supply of 1.8 V and the 4.167 GHz frequency, the power dissipation is 597mW, 478 mW, and 410 mW, and the chip area is 0.118 mm2, 0.087 mm2, and 0.075 mm2, respectively.

Moments are utilized in image processing for pattern recognition, machine vision and numerous feature extraction techniques. Due to computational complexity, it is difficult to use high order moments in real time processing. This paper presents the design of two new architectures for real time computation of moments, up to order 14, M00 to M77, in gray level images, based on parallel systolic arrays and pipelining technique, using a 0.18μm CMOS technology.Implementation of the moment processing element (MPE) of the first architecture illustrates a processing speed of 125 frames/s for 1024×1024 grey-level images. The maximum operating frequency and the power consumption for an architecture with 5 elements is 133 MHz and 14.36 mW, respectively. Since the design is very low power, the number of parallel MPE’s can be easily increased. Simulation shows that with 11 parallel MPE’s, the first 49 moments of 1024×1024 image are computed with the speed of 30 frames/sec.To further decrease the latency of the first architecture, the second architecture is proposed, in which the add operation is performed only with a single adder and a compressor. Simulation shows that the latency of the second architecture is 3.3 times lower than that of the first architecture. Implementation of the second architecture illustrates the maximum operating frequency and the power consumption of 125 MHz and 58.34 mW, respectively. Operating frequency and power consumption of the second architecture is approximately the same as that of the first architecture which befit real time applications.