محسن تمدن خشکناب

In this paper a Time-Amplifier, one of the most significant blocks of the time domain signal processing modules will be designed and simulated. Time domain signal processing is one of the most forerunner alternatives for the amplitude domain signal processing specially in nowadays nanotechnology devices. The main core of a time mode processor is a Time-to-Digital Converter (TDC). Increasing the resolution of the TDC, the processing of the signal is performed with higher quality. One of the most challenging efforts is the processing of two signals with very small time difference between their edges. Recently, some new techniques are proposed to overcome this significant problem. One of these techniques is amplifying the time difference, before employing it into the time mode signal processor or a TDC. Regarding this bottleneck, in this paper a high resolution, high gain, highly linear time amplifier (TAMP) with a large dynamic range (DR) is designed. The pre-detector of this TAMP, is a novel digital Pulse-to-Edge Converter (PEC) which also can operate in high frequencies. This TAMP is utilized in a proposed TDC in order to give one important utility of the circuit. The proposed topology is designed in a 0.18μm CMOS process and simulated via ADS2009 and Cadence® (Spectre RF). The simulation results illustrates the total power consumption is 1.7 mW, occupied area of the chip is below 0.35 mm2, time resolution is 5 psec, gain of the TAMP is approximately near to 200 s/s and the total linear DR of the TAMP is almost 350 psec.