میدیا رشادی

Spatio-temporal (ST) clustering is a relatively new field in data mining with great popularity, especially in geographic information. Moving objects are a type of ST data where the available information on these objects includes their last position. The strategy of performing the clustering operation on all-time sequences is used for clustering moving objects. The problem with density-based clustering, which uses this strategy, is that the density of clusters may change at any point in time because of the displacement of points. Hence, the input parameters of an algorithm like DBSCAN used to cluster moving objects will change and have to be determined again. The DBSCAN-based methods have been proposed so far, assuming that the value of input parameters is fixed over time and does not provide a solution for their automatic determination. Nonetheless, with the objects moving and the density of the clusters changing, these parameters have to be determined appropriately again at each time interval. The paper used a dynamic multi-objective genetic algorithm to determine the parameters of the DBSCAN algorithm dynamically and automatically to solve this problem. The proposed algorithm in each time interval uses the clustering information of the previous time interval to determine the parameters. Beijing traffic control data was used as a moving dataset to evaluate the proposed algorithm. The experiments show that using the proposed algorithm for dynamic determination of DBSCAN input parameters outperforms DBSCAN with fixed input parameters over time in terms of the Silhouette and Outlier indices.

Networks-on-Chip (NoC) is an effective solution to inside on-chip communication problems. In recent years, the advancement of silicon industry and also the production of Carbone Nanotube antennas (CNTs), it is possible to use wireless antennas in the network on chip. This new communication structure is called a Wireless Network on Chip (WiNoC). Using the wireless antenna in multi-core chips led to the reduction in the latency and power consumption. In spite of higher bandwidth of the WiNoCs compared to wire NoCs; their performance can decrease significantly in absence of an effective flow control mechanism.In this paper, the flow control problem is investigated by using a mathematical model in the WiNoC. The aim of this study is showing a correct analysis of cores behaviors with the subject to capacity constraints of links and flow rates. The simulation results of traffic pattern in the WiNoC show that the proposed flow rate control algorithm has been able to control and adjust the flow injection rate of each transmitter with acceptable convergence

A multi-processor architecture was proposed to address power consumption limitations in chips in order to increase performance and lower power consumption. In this architecture, the highest power consumption comes from the chip connections. Optical connections can reduce power consumption and increase performance via a new architecture called photonic network-on-chips, which are capable of utilizing the benefits of optical signals and elements for data transfer. This paper proposes a 4×4, non-blocking photonic switch to improve physical layer parameters by increasing photonic network performance. The insertion loss and energy dissipation of the proposed switch were compared to three switches: Original, StraightPath, and Symmetric switches. The results indicated that, in a mesh topology, the proposed switch reduced loss for the GTC, Cactus, Tornado, and MADbench by 28.22, 24.46, 28.72, and 29.20%, respectively, when compared to the Original switch. According to PhoenixSim simulation results, the proposed switch reduced insertion loss and energy dissipation in photonic network-on-chips when compared to the three comparison switches.

Many of processing cores integrated on chip have high speed; Photonic Network-on-Chips is one of the simple methods to solve addressing problem in huge interconnection networks. For this reason, multiprocessing chips with high performance and high bandwidth are needed in future. Photonic Network-on-Chips is a new generation of Network-on-Chip which can solve the traditional networks limitations and has many advantages such as high communication bandwidth, low transfer latency and power consumption. On the other hand, Photonic Network-on-Chips has many challenges. Routing photonic data on photonic layer is one of the important challenges, because the path selection has influence to optical loss factor. In this paper, deadlock free adaptive turning models routing algorithm, circuit switching and different traffic pattern to reduce optical loss on photonic layer with 5port deadlock free router and 2-D Mesh topology is proposed. Finally, we compare our simulation result with similar algorithm such as dimension order XY routing algorithm and the resulted improvement is shown.