جستجوی مقالات مرتبط با کلیدواژه "ambipolar current" در نشریات گروه "شیمی"

In this paper, a new Nano-Scale structure of dual material gate oxide stack-double gate TFET (DMGOS-DG TFET) with the inclusion of the dielectric pocket (DP) in the drain region is proposed. Hence the gate consists of three parts, named M1, M2, and M3 with work functions ϕM1, ϕM2, and ϕM3 respectively. The work function engineering with the gate oxide stack (SiO2 as the bottom layer and HfO2 as the top layer) improves ON current, leakage current, and ambipolar behavior. In addition, the dielectric pocket (DP) has been used in the drain region to achieve better ambipolar performance. Moreover, it is found that in comparison with the low-k DP (SiO2), the presence of the high-k DP (HfO2) provides a lower ambipolar current due to the greater depletion width in the drain region. Furthermore, the ambipolar behavior of the DP-DMGOS-DG TFET structure has been investigated by changing the length and thickness of the high-k DP. Finally, the comparative analysis of DMGOS-DGTFET and high-k DP-DMGOS-DG TFET on high-frequency performance reveals that DP inclusion reduces the gate-to-drain capacitance, which leads to the improved cut-off frequency.

In this study, a new nanoscale U-shaped tunnel field-effect transistor (US TFET) structure is proposed. In order to start the design process, the drain region of the conventional US TFET is divided into two distinct parts with N+ and N- doping which is named the drain doping engineering (DDE). It is considered that the tunneling barrier at the channel-drain junction is increased and consequently the ambipolar current is decreased considerably. To continue the design process, the dual work function (DW) in the DDE-US TFET has been used to ameliorate the DC characteristics and the cutoff frequency. Moreover, we have used the metal implant (MI) in the source-side oxide of DDE-DW-US TFET as a technique to improve the device for high-frequency and low-power applications. The 2-D TCAD simulation results not only indicate the superiority of the proposed structure (DDE-DW-MI-US TFET) compared to others in terms of the high-frequency performance, but also illustrate the improvement of the DC parameters. Finally, the proposed device has been investigated by increasing the length of implanted metal in the source-side oxide. It is found that selecting the appropriate length contributes significantly to improve high-frequency performance.

This study investigates geometrical variability on the sensitivity of the junctionless tunneling field effect transistor (JLTFET) and Heterostructure JLTFET (HJLTFET) performance. We consider the transistor gate dielectric thickness as one of the main variation sources. The impacts of variations on the analog and digital performance of the devices are calculated by using computer aided design (CAD) tools. The gate oxide thickness is varied uniformly from right to left and vice versa and the performance of devices are analyzed. It is shown that changes in the geometric dimensions of the devices improves some electrical parameters and degrades others. Finally, we use the oxide thickness variation advantage and implement the oxide pocket close to the drain-channel interface for proposing of the pocket in narrower drain side oxide HJLTFET (PNS-HJLTFET)