جستجوی مقالات مرتبط با کلیدواژه « full adder » در نشریات گروه « فنی و مهندسی »

Full adder cell is an important module in processing systems and has various applications and is used in most arithmetic circuits. Therefore, the design of high-performance Full adder cell will improve the performance of the whole system. On the other hand MOSFET technology has encountered challenges due to the scaling down of transistors. New technologies can be used to solve this problem. Carbon nanotube field effect transistors (CNFETs) are one of the appropriate alternatives to MOSFET. The threshold voltage of these transistors can be easily adjusted by tuning diameter of carbon nanotubes, which makes it very appropriate for designing multi-valued logic circuits. In this paper we have tried to provide a quaternary full adder circuit based on carbon nanotube field effect transistors that is more efficient so that in addition to speeding up the operation, productivity and reducing power consumption are also considered. The proposed design is simulated using the HSPICE Synopsis simulator and compared with previous designs. Simulations have also been performed to investigate the effect of process, temperature and voltage. The results show that the proposed design is faster than previous designs and reduces the PDP parameter by about 75% compared to the best reported design.

With the design of circuits at the nano-scale and observation of the problems of CMOS technology, designers are seeking suitable alternatives for this technology. Quantum-dot Cellular Automata (QCA) is one of these proposed technologies, which has attracted researchers' attention due to its high speed and low power consumption. On the other hand, the Gate Diffusion Input (GDI) method is an approach to improve power and area efficiency, which has led to higher speed, less power loss, and reduced complexity in Boolean functions through the use of fewer transistors. Furthermore, the adder, as a fundamental computational circuit in the design of digital systems, is of special importance. In this paper, a half-adder circuit, a half-subtractor circuit, and three new adder circuits in QCA technology have been designed and improved with the help of the GDI block. Simulation of these circuits using the QCADesigner software in 18-nanometer technology demonstrates the advantages of simultaneously using QCA technology and the GDI method. The results of the comparison and evaluation of the proposed circuits relative to the best existing adder indicate a reduction of about 55% in the occupied area, a significant decrease in the number of cells, and a delay that is equal to or less than 28% compared to existing works.

Today, CMOS technology circuits are faced with basic challenges in parameters such as speed, frequency, and power consumption due to the impossibility of further reducing the dimensions. In this regard, one of the solutions proposed by the researchers is to introduce alternatives to this technology, among which we can mention the quantum-dot cellular automata technology (QCA). A lot of research has been done to design digital circuits in QCA technology. Since the full adder circuit is one of the integral parts of a arithmetic and logic unit, it is one of the circuits that is of interest to designers familiar with QCA technology. Therefore, in this paper, the design of a new full adder is prioritized. In this article, using a three-input XOR gate and a three-input majority gate, a full adder is designed that has 35 cells, an occupied area of 0.03 micrometer square and 2 delay clock regions. The proposed full adder has made good improvements in terms of the features compared to the previous designs. To confirm the function of the proposed structure, simulation has been done by QCADesigner software.

In this paper, we limit our attention to full adders based on the GDI method, circuits that are commonly used in high-speed circuits and are more prone to noise. So far, a comprehensive review on noise immunity and ambient temperature change of full adders based on the GDI method has not been presented, and most of the studies have compared their proposed design with other full adders, which are mainly not based on the GDI method. These full adder cells were evaluated by various simulations such as supply voltage change, capacitive load change, ambient temperature change and process-voltage-temperature (PVT) changes in 45 nm CMOS technology. A noise immunity curve (NIC) was derived for full adder cells to identify better-performing full adder cells. The unity noise gain (UNG) was also investigated to evaluate the noise. Finally, a comprehensive comparison was made in terms of propagation delay, power consumption, power-delay product (PDP), voltage swing, sensitivity to process changes and noise for full adders based on the GDI method. The obtained results can be useful in the decisions of integrated circuit designers to choose the appropriate structure of the full adder based on the GDI method

In today's electronic and digital world, increasing demand for portable systems has led the electronics industry and chip design technology to reduce power consumption methods, and therefore power consumption has become an important criterion in this field. Also, increasing the speed of chips and reducing the propagation delay of circuits has always been an important goal of digital design engineers. Since the Adder element is one of the important elements in many digital systems, so today various Adders with different technologies and design approaches have been proposed, each of which has certain advantages and disadvantages. This paper presents a low-power single-bit full-adder cell design that is based on pass-transistor logic.This circuit is used in the arithmetic logic units of digital signal processors and also in several electronic and digital communication systems that operate within the frequency range of in 1GHz. The proposed cell exploits the pass transistor techniques and XOR-XOR structures to improve the design parameters namely power consumption, propagation delay, power–delay product, and the number of transistors. The proposed circuit is designed using 180nm CMOS technology and the simulation results show that for a supply voltage of 1.8V, the power consumption, delay, and power–delay product have been achieved as 83 W, 89ps, and 7fJ respectively.

In this paper, full adder circuit with Hybrid-CMOS logic style is proposed which is a combination of pass transistors and transmission gates and N & P type transistors. For design full adder circuitry using FINFET transistors, BSIM-CMG model, Dual-gate and bulk FINFET structure using 16nm Gate length and HSPICE simulation. due to the structure and architecture of the FINFET transistors, the effect of changes in thickness and height and the number of FINs on the Drain current of the FINFET transistor and output parameters such as average power dissipation and propagation delay of the full adder cell and also the effect of changes in inputs frequency of full adder are investigated. According to the simulation results, with increasing thickness and height and the number of FINs, average power dissipation increases and propagation delay decreases, and vice versa. As well as increasing the operating frequency up, average power dissipation increases.

Novel digital circuit design methods are vital due to the significant increase in data that requires fast processors. No doubt, power consumption is an essential factor in electronic devices. Hence, the design of low-power, area-efficient, and high-performance circuits is crucial. Approximate computing as a promising method for designing efficient circuits in addition to applying CNTFETs can be an excellent solution for the concerns mentioned above. In this article, according to the full adder’s importance in DSP processors, a new approximate full adder based on 32nm Stanford CNTFET model is proposed and optimized in terms of power consumption, delay, PDP, and the number of transistors. HSPICE is applied to compare this new design with state-of-art articles. The simulation results indicate that the proposed design has not only the least delay but also shows an 87% improvement in PDP achieved. Various simulations applying different load capacitors, supply voltages, and process variations demonstrate the acceptable functionality of proposed approximate full-adder in different situations. Image addition simulation using MATLAB is applied to assess the performance of the proposed design in a real error-resilient application.

Quantum dot cellular automata (QCA) as an important technology with minimal size, high speed, low latency and power consumption is suitable replacement for semiconductor transistor technology. The growing demand for observability and testability attracts more research on it. A full adder circuit is a basic unit in digital arithmetic and logic circuits. In this paper, a unique structure for testable full adder is presented in QCA. The implementation of the full adder circuit with the structure of the Built In-Self Test (BIST), its observational capabilities and its intermediate component controllability increase the reliability and the test capability of other designed circuits based on this. All of inputs in the proposed have testability and controllability capability and the middle nodes have observability feature. This design in contrast to its counterparts uses three-layer scheme and surpasses the best previous layer designs in terms of area, delay and complexity. The simulation results using QCADesigner software confirmed that the presented circuit works well and can be used as a high-performance design in QCA technology.