جستجوی مقالات مرتبط با کلیدواژه "h∞" در نشریات گروه "برق"

In this paper, the optimal sizing of a distributed generation system with a combined solar/battery power is presented using the PSO algorithm. Given that the power generation in solar panels depends on solar radiation, the battery energy storage in the grid-connected state allows the storage of the generated power of photovoltaic panels and the sale of power to the grid during the night-time peak consumption hours - when electricity costs are high. Economic modeling of photovoltaic panels, batteries and converters is presented. Based on the optimization and sensitivity analysis, the use of photovoltaic panels for power conversion and electricity sale to the grid is highly dependent on the price of photovoltaic panels and the price of grid electricity and is acceptable.

In this paper, the evaluation of the installation location and optimal location of distributed generation plants and capacitors in radial distribution systems in order to reduce losses and improve voltage profile has been studied. Simulation has been performed to minimize the active power loss index, reactive power loss, and voltage profile and multi-objective optimization has been performed using the genetic algorithm method. In this paper, the effects of DG and capacitor placement have been first examined separately and then simultaneously. In the simultaneous placement mode, 1- the case where all equipment is placed on one bus and 2- the case where equipment is placed on different buses have been studied. Load distribution was performed using the Newton-Raphson method and then the simulation was tested on two standard IEEE 33 and 69 bus networks. The results show that there is a significant reduction in losses and the voltage profile is also improved.

In the last three decades, after the significant increase in fuel prices, the importance of alternative fuels, increasing energy efficiency, and reducing environmental pollution, the desire to use new technologies, including cogeneration of electricity and heat, has increased. In conventional methods for meeting electrical and thermal needs, electricity is supplied from the national distribution network and heat is supplied by burning fuel in boilers and heat- generating equipment in a separate production method. In this method, a significant amount of energy is wasted in various ways through hot exhaust gases from chimneys, cooling towers, condensers, coolers in internal combustion engines, and also through losses in the distribution and transmission of electricity in the national electricity grid. Most of this heat can be recovered and can be used to provide thermal energy. On the other hand, the electricity produced in this method is centralized (power plant) and involves a lot of energy losses. [1] In this article, we will introduce the types of cogeneration systems, introduce their advantages and disadvantages, and also introduce their applications.

In this research, a 16-bit multi-mode second-order Delta-Sigma Modulator-Digital-to-Analog Converter (DSM-DAC) with a time-interleaved (TI) structure operating at a center frequency of 4 GHz and a bandwidth of 20 MHz has been implemented using VHDL on an FPGA platform. The proposed architecture utilizes a single clock frequency for generating RF signals. The second-order DSM is reconfigurable, offering three filter modes: LP, BP at Fs/4, and HP for signal synthesis. Since the coefficients remain simple for all modes, multiplication operations can be achieved using a shifter block. To investigate the effect of duty-cycle-error (DCE) and its compensation, various error values are applied to the modulator and compensation is performed. A novel solution is proposed to overcome the DCE by adjusting the filter and unilaterally narrowing the signal passband without adding extra hardware complexity. This approach significantly enhances the SNDR and SFDR of the DSM output, even for the BP mode. Another challenge is the mismatch error in DAC cells. This error is simulated and compensated using two methods DWA and SDEM. Simulation results in ISE demonstrate that the SNDR values for LP, BP, and HP modes are 106.10, 105.65, and 104.95 dB, respectively.

Motor Imagery is a mental process that includes preparation for movement. The brain interface system intends to prepare direct connectivity between the brain and the computer to be aware of the requests of an individual and use them as a control signal for external devices. Motion imaging events occur in the three main frequency bands: beta, mu, and gamma. After preprocessing the EEG data, the next step is to apply various types of filters in order to reduce any residual noise present in the signal. Numerous functional imaging studies showed that motion-imaging results from the specific activation of neural circuits involved in the early stages of motor control. Studies have shown that the CSP algorithm performs better than other algorithms. Due to the lack of a suitable frequency band, the results of the frequency-dependent CSP method are not satisfactory, so the CSSP is similar to the FIR filter, but since this filter does not have all the coefficients of an FIR filter, the presence of noise in the EEG signal can lead to suboptimal definition of the frequency filter. The CSSSP algorithm was used to solve this problem. With using sequential feature selection for feature extraction, it was revealed that CSSSP performance has been better compared to the CSP and CSSP in most cases and the average accuracy was 92.55%.

One of the basic challenges in high-density integrated circuits is loss of power consumption, which is caused by presence of transistors in circuits and causes the temperature of the circuit to increase. The design of digital circuits in a reversible way can be used as one of efficient approaches to solve this challenge. In addition, the design of parity-preserving reversible circuits can be very effective in detecting faults in circuits. Dividers are used as one of the most widely used circuits in digital computing systems. Divider circuits include an adder, a multiplexer and two sequential register and parallel-in to parallel-out left shift register circuits. This paper is presented a new and efficient design of a parity-preserving reversible non-restoring divider. For this purpose, first, a parity-preserving reversible D-latch is proposed. second, a parity-preserving reversible n-bit register is presented using the proposed reversible D-latch. Third, a parity-preserving reversible (n+1) bit shift register using the proposed reversible D-latch and other reversible gates is proposed. Finally, a parity-preserving reversible n bit divider is developed based on the non-restoring algorithm. The results of comparisons show that the proposed circuit is superior in terms of evaluation criteria of reversible circuits such as quantum cost, number of constant inputs and number of garbage outputs compared to previous works.