جستجوی مقالات مرتبط با کلیدواژه « Carbon Nano Tube Field Effect Transistor » در نشریات گروه « برق »

Due to the increase of processing data, processing systems should be designed to occupy less space. The enlargement of the processing systems has caused the growth of the data size, on the other hand, the problems of miniaturization of metal-oxide semiconductor field effect transistor MOSFET have faced many problems for the designers of processing circuits, the idea of replacing binary processing circuits with multi-valued level processing circuits. It reduces connections between systems and reduces space consumption. Because the implementation of multi-level processing circuits with MOSFET technology is very complicated and problematic, a suitable alternative for MOSFET is carbon nanotube field effect transistor (CNTFET) technology, which has many advantages such as the possibility of making transistors It has a different threshold voltage, which reduces design challenges in the implementation of multi-level systems. In this article, the structure of the transistor level of single-digit quaternary and multi-digit comparators is presented. Transistor level circuits are presented along with circuit techniques. The simulation results also show that the amount of propagation delay and power consumption in the single-digit quaternary comparator is 17.3 picoseconds and 4.59 microwatts, respectively, and the PDP index of this comparator is 79.2 aJ. All simulation results of proposed comparators in this article have been obtained using carbon nanotube field effect transistors and 32 nm technology in HSPICE software.

The increasing growth of processing data size in digital systems has increased the number of connections between processing systems, which requires a lot of space to establish communication with other processing systems. The design and implementation of multi value level processing systems reduce the size of processing data. On the other hand, the important issue in the implementation of multi-level processing systems is problems and complications of design. The use of substitute transistors such as nano-carbon tube field effect transistors instead of metal oxide semiconductor field effect transistors while reducing design problems in nano dimensions is functionally more suitable than metal oxide semiconductor field effect transistors. In this article, a report on the implementation of a multi inputs full ternary comparator based on carbon nanotube field effect transistor technology is presented. The implementation report of the one digit and two-digit ternary comparator at the transistor level has been done in this article, and the implementation method of the multi-input ternary comparator has also been presented. The simulation results in the HSPICE software environment show that the power consumption of the proposed comparator is 0.55 µW and the propagation delay time is 70 ps. In addition, the proposed comparator has been implemented based on 32 nm carbon nanotube field effect transistors technology.

In this paper, the transistor level of single-ended and differential low-power sample-hold is presented based on carbon nanotube field effect transistor technology using the advantages of second generation current conveyor blocks. The switching operation in the proposed sampl and holds is based on the structure of the second generation current conveyor, which means that it has the same function as the analog current-conveyor switches.The implementation of the proposed the sample and hold blocks with using advantages of carbon nanotube field effect transistors improves the performance sampl and hold circuit. The proposed sample and hold circuits have very low power consumption and high operating speed, and it also does not require a non-overlapping clock pulse signal. These proposed circuits have been implemented and simulated in HSPICE software using 32-nanometer carbon nanotube field effect transistor technology. The simulation results show that the power consumption of the differential sample and hold circuit is 13.45 μW, also the ENOB value of the differential sample and hold circuit for the sampling frequency of 2 GHz and the input frequency of 20 MHz is 11 bits. The FOM index of the proposed circuit is 0.61×10-6 (nJ/Bit.Samples).

The full adder circuit is one of the most significant and prominent fundamental parts in digital processors and integrated circuits since it can be used for implementing all four basic computational functions including: addition، subtraction، multiplication، and division. so، in this paper a new low power and high performance full adder cell has been proposed with the benefit of using carbon nano tube field effect transistors. The proposed design contains 12 CNTFET transistors which are connected in pass transistor logic style to make the desired functionality. Carbon Nano Tube Field Effect Transistor (CNTFET) has modified electrical characteristics such as low power consumption and high speed in comparison with MOSFET transistor; The proposed design is simulated using Hspice software based on CNTFET model and 0. 65V supply voltage. the simulations are done considering three different frequencies، and three different load capacitors. The simulation results، which demonstrated in tables and diagrams، proved the superiority of proposed design in terms of power consumption and performance (PDP) compared to the existing counterparts.