جستجوی مقالات مرتبط با کلیدواژه « Digital to analog converter » در نشریات گروه « برق »

Performance of the current steering digital to analog converters are limited by transistors channel width and length mismatches and their Threshold and Early voltage variations due to fabrication process errors. Although there are several ways to reduce errors due to element mismatches, however these errors cannot be completely eliminated. In this paper, Distributed MOS Transistor Technique is utilized which facilitates Dynamic Element Matching implementation capability in Binary Digital to Analog Converter. The proposed technique reduces the errors due to element mismatches and also load voltage variations needless of high power consumption and complex circuitry. This technique operates based on random selection of unit current blocks among specific number of available current units. To make the generated code as random as possible, a random code generator, full adder and 4*16 decoder have been used. This technique is realized in a 10-bit digital to analog converter with 180 nm CMOS technology. The LSB current is 500nA and supply voltage is 1.8v and the power consumption of this converter is 14.6 mW and SFDR of DAC is achieved 60.27 dB based on simulation result with Cadence Spectre software.

This paper presents an 8-bit analog-to-digital converter (ADC) designed using an improved successive approximation Register(SAR). The proposed structure of the SAR converter uses an integrator embedded with a digital-to-analog converter (DAC). The presence of an integrator at the input of the ADC eliminates the need for a sample and hold circuit and is used to generate different voltage levels in the DAC. Thus, the successive approximation algorithm in the proposed structure has been modified to provide the required voltage levels with a few number of capacitors in the DAC. Therefore, the complexity of the circuit is reduced and less silicon is occupied due to a reduced capacitive array in DAC. The proposed ADC completes the analog input to digital code conversion in 10 clock pulses. In order to study the proposed method, the SAR ADC is designed and simulated at the transistor level in 0.18 μm CMOS technology at 1.8 V supply voltage. The simulation results show that the ratio of signal to noise and distortion (SNDR) for input bandwidth of 640 kHz is 48.3 dB, effective number of bit (ENOB) and power consumption are 48.3 dB, 7.74 bits and 0.85 mW, respectively.

This paper presents the design and implementation of a digital-to-analog converter with a frequency of one billion samples per second and a resolution of 12 bits in the standard process of 0.35um CMOS technology. This included designing new circuits that converted the converter, with good INL results (0.7LSB for 8 bits and 0.8LSB for 12 bits). Also, SFDR with Fsig = 125Meg and Fs = 500Meg is about 73dB and for Fsig = 125Meg and Fs = 1G is about 60dB by calculating the total capacitance of the layout. Total power consumption 180mw and works with 3.3v and 2v power supplies. According to the designed layout, the occupied surface of the chip is 0.313mm2 and four metals and two polyes are used and the simulation results are done by Hspice software.