جستجوی مقالات مرتبط با کلیدواژه "fpga" در نشریات گروه "فناوری اطلاعات"

A dual stage system architecture for face detection based on skin tone detection and Viola and Jones face detection structure is presented in this paper. The proposed architecture able to track down human faces in the image with high accuracy within time constrain. A non-linear transformation technique is introduced in the first stage to reduce the false alarms in second stage. Moreover, in the second stage pipe line technique is used to improve overall throughput of the system. The proposed system design is based on Xil inx’s Virtex FPGA chip and Texas Instruments DSP processor. The dual port BRAM memory in FPGA chip and EMIF (External Memory Interface) of DSP processor are used as interface between FPGA and DSP processor. The proposed system exploits advantages of both the computational elements (FPGA and DSP) and the system level pipelining to achieve real time perform ance. The present system implementation focuses on high accurate and high speed face detec tion and this system evaluated using standard BAO image database, which include images with different poses, orientations, occlusions and illumination. The proposed system attained 16.53 FPS frame rate for the input image spatial resolution of 640X480, which is 23.4 times faster detection of faces compared to MATLAB implementation and 12.14 times faster than DSP implementation and 2.1 times faster than FPGA implementation.

The mapping of DNA subsequences to a known reference genome, referred to as “short-read mapping”, is essential for next-generation sequencing. Hundreds of millions of short reads need to be aligned to a tremendously long reference sequence, making short-read mapping very time consuming. Day by day progress in Next-Generation Sequencing (NGS) is enabling the generation of DNA sequence data at ever faster rates and at low cost, which means a dramatic increase in the amounts of data being sequenced; nowadays, sequencing nearly 20 billion reads (short DNA fragments) costs about 1000 dollars per human genome and sequencers can generate 6 Terabases of data in less than two days. This article considered the seed extension kernel of the Burrows-Wheeler Alignment (BWA) genomic mapping algorithm for accelerating with FPGA devices. We have proposed an FPGA-based accelerated implementation for the seed extension kernel. The Smith-Waterman algorithm is used during the seed extension to find the optimum alignment between two sequences. The state-of-the-art architectures use 1D-systolic arrays to fill a similarity matrix, based on the best score out of all match combinations, mismatches and gaps are computed. The cells on the same anti-diagonal are calculated in parallel in these architectures. We propose a novel 2-dimensional architecture. Our new modified algorithm is based on two editing and calculating phases. In each step of calculation, some errors may occur in which all the cells on the same row and the same column are computed in parallel and, thereby, significantly speed up the process. Needless to say, these probable errors will be omitted before the next step of calculation begin. Our simulation results show that the proposed architecture can work with up to 312 MHz frequency in Synopsys Design-Compiler for 180-nm CMOS technology and be up to 570x and 1.4x faster than the software execution and the 1D-systolic arrays, respectively.

Recently, the growth of convolutional neural networks in various scientific fields can be seen dramatically. The use of various software and hardware techniques in advancing this process provides the platform for increasing research and finding different solutions to increase the efficiency and optimization of this method. One of the important techniques in the field of neural networks is the Generative Adversarial Networks (GAN) and its implementation on FPGA accelerators. In this paper, we will provide an overview of the growth process of convolutional neural networks with using GAN technique and its implementation on FPGA accelerator over two years. In this series we intend to follow some of the most primitive projects starting almost 2017 and by the end of 2018, where significant progress can be made. In this work, we review five papers, the first of which is presented in 2017 and the other four in 2018. The method of comparing these articles is characterized by four distinct perspectives: Optimal utilization of accelerator resources, application of specific techniques, analysis of generated data, and finally the speed of execution in FPGA-based systems is a requirement. Finally, we discuss the advantages and disadvantages of these designs to optimize and improve their performance.

P. Elias proposed convolutional coding at 1955. Convolutional encoders have very simple structure but their decoders are very complex and power consumer. Power consumption and error correction of Convolutional Codes, will be enhanced by increase in their constrain length, therefore there is always a trade-off between Power consumption and error correction. In Convolutional Codes, the code specifications remain constant in each frame. If the specifications are changed during each frame in a code, a new code with new performance and specifications is created. This paper, aims to evaluate this issue for the first time and compare its performance with Convolutional Codes. This new code is named “Decimal Convolutional”. If in a decimal convolutional code, constrain length is changed during each frame, the generated code will be a convolutional code with “decimal constrain length”. In this paper, a convolutional code with decimal constrain length is introduced, encoder and Viterbi decoder structure is explained for it and its specification is compared with convolutional code. Using this code, an optimized constrain length can be obtained and relative power consumption of decoder can be also reduced. The proposed design blocks are described by VHDL and they are implemented on Xilinx Spartan3, Xc3s400 FPGA chip.

In communication systems, ensuring correct information reception is very important, Error Correction Coding methods have been developed in order to achieve this goal. Convolutional Code is used in Wireless, Satellite, mobile phones and Deep-Space communications, it is one of the most powerful Error Correction code, and the Viterbi algorithm is robust way to decode it. Power conception and speed are two important feature of Viterbi decoders, in many communications the power consumption is most important. In this paper, by removing extra decoding cycles, the SMU registers are reduced by 20%, the power consumption reduced by 14.5% and the speed increased 6 times without error correction performance loss. The proposed design is described by VHDL and it is implemented on Xilinx Spartan3, Xc3s400 FPGA chip.

in this paper we have presented the implementation of radar digital quadrature channel receivers in FPGA. Utilizing direct digitalization due to avoid improbable matching in producing in-phase (I) and quadrature (Q) signals, is greatly respecting in every modern system but this merit needs some considerations which are highlighted in the current paper. Two factors resource and maximum frequency for hardware implementation of proposed algorithm utilizing Virtex-5 ML506 are evaluated and compared with the customary algorithm of analog and digital receivers which generally utilize two mixers, lowpass filters and analog to digital converters for down converting signal from intermediate frequency to baseband. Also in this paper some simulations for different examples are illustrated.

Median filters are commonly used for removal of the impulse noise from images. De-noising is a preliminary step in online processing of images, thus hardware implementation of median filters is of great interest. Hence, many methods, mostly based on sorting the pixels, have been developed to implement median filters. Utilizing vast amount of hardware resources and not being fast are the two main disadvantages of these methods. In this paper a method for filtering images is proposed to reduce the needed hardware elements. A modular pipelined median filter unit is first modeled and then the designed module is used in a parallel structure. Since the image is applied in rows and in a parallel manner, the amount of necessary hardware elements is reduced in comparison with other hardware implementation methods. Also, image filtering speed has increased. Implementation results show that the proposed method has advantageous speed and efficiency.