جستجوی مقالات مرتبط با کلیدواژه « hafnium oxide » در نشریات گروه « مواد و متالورژی »

This paper presents a novel design and analysis of a Low-k Source side Asymmetrical Spacer Halo doped Nanowire TFET. The utilization of high-k hafnium oxide spacer materials in TFET enhance electrostatic control and minimize short-channel effects in nanoscale devices. However, the performance of dynamic circuits suffers with higher fringe capacitance brought on by high-k spacers. Our method focuses on reducing gate capacitance by optimistic utilization of high-k spacer material. The proposed device is constructed in SILVACO TCAD software and results states that the use of Low-k material as silicon dioxide at the Source-side spacer in halo-doped nanowire TFET design results in significantly reduced gate-capacitance and intrinsic-delay. For this proposed TFET device, the circuit performance of advanced nanowire structure can improve drain current characteristics and analog characteristice.  The proposed device exhibits better performance as compared to other spacer engineering devices. As a consequence, the suggested device appears as a strong suitable device for low power digital applications.

This paper investigates the electrical behavior and performance of a  Dual Metal Gate Overlap on  Drain Side Tunnel Field Effect Transistor with Spacer (DMG-ODS-TFET) in 10 nanometer technology. In this design, the utilization of two different metals to create the gate effectively maintains electrostatics and minimizes gate leakage current. This structure is formed by silicon dioxide and hafnium oxide as dielectric materials. The drain current characteristics such as subthreshold swing, on-state current, off-state leakage current, and transconductance are calculated for the proposed device using the available two-dimensional numerical device simulator silvaco tool. The characteristics of the proposed device vary with changes in channel length, doping concentrations of the drain and source, and the thickness of the oxide layer. This structure shows a lower off current, and better on-to-off current ratio with improved drain current. Consequently, the proposed design effectively balances gate control and leakage current, resulting in superior to conventional and dual metal gate devices. Based on improved performance parameters, this proposed structure is suitable for high-frequency applications.

In this work, a Symmetrical Dual Gate Tunnel Field Effect Transistor (SDGTFET) is proposed with gate dielectric materials in 10nm technology. The electrical performance parameters of this proposed device are investigated using technology computer aided design (TCAD) simulator. The new SDGTFET employing with high-k dielectric material such as hafnium oxide (HfO2) and interfacial layer (IL). The 2nm HfO2 with 30 dielectric constant is used between the interfacial layer and the metal gate on both sides of the device. The variation of the drain current with the varying of gate length, effective gate materials and effective oxide layer thickness of the device is evaluated in this work. By optimizing the proposed device with gate dielectric material the on current gets ∼4.2 times enhanced and the averaged subthreshold swing (SSavg) becomes reduced from 90.2 mV/dec to 53.8 mV/dec. Therefore, the SDGTFET structure has better performance than single material and double material TFET and shows a lower ambipolar current and a better on current to off current ratio.

This paper presents a design and analysis of a Hetero Dielectric Dual Material Gate Underlap Spacer Tunnel Field Effect Transistor, aiming to enhance device performance and overcome inherent limitations. The proposed design incorporates a hetero dielectric gate stack, which consists of two distinct dielectric materials such as high-k-dielectric material as hafnium oxide (HfO2) and low-k dielectric material as silicon dioxide (SiO2). With different permittivity values. By selecting these materials, the gate stack can effectively modulate the electric field distribution within the device, improving electrostatic control and reducing ambipolar conduction. Furthermore, an underlap spacer is introduced in the presented structure to create a physical separation between the source and the channel regions. This spacer helps in reducing the direct source-to-drain tunneling current, enhancing the Ion/Ioff current ratio and reducing the subthreshold swing. Additionally, the underlap spacer enables improved gate control over the tunneling process. The proposed Tunnel Field Effect Transistor design is thoroughly analyzed using numerical simulations based on the technology computer-aided design (TCAD) simulator. Performance metrics as the on-state current (Ion), the off-state current (Ioff), ION/IOFF ratio, drain conductance (Gd) and transconductance (Gm) to assess the device's performance. Therefore, these improvements contribute to lower power consumption and improved circuit performance, making it a promising device for low-power applications.

A Hetero Dielectric Tunnel field effect transistor with the spacer on both sides of the gate is proposed in this paper. The performance and characteristics of Hetero Dielectric Tunnel field effect transistor using the ATLAS Technology Computer-Aided Design in 5nm regime were analyzed. The band-to-band tunneling leakage current will be reduced by introducing heterojunction and hetero dielectric spacer material in the proposed structure. In Hetero Dielectric Tunnel field effect transistor, double metal gate and high-k dielectric spacer improves high on the current and subthreshold swing. The high-k dielectric Hafnium oxide spacer is placed on both sides of the source and drains to import the tunneling mechanism. The proposed device in the 5nm node has improved DC characteristics such as a High ON-state current of 1.68 x 10-5 Amp & OFF-state Current reduced from 7. 83x 10-11 Amp to 5.13 x 10-12 Amp and ION / IOFF ratio has increased from 3.22 x 105 to 3.27 x 10  compared to conventional dual gate Tunnel field effect transistor. Therefore, this device is suitable for low power applications