The FPGA Implementation of an Efficient Elliplic Curve Cryptographic Process over GF(2163)

A new and highly efficient architecture for elliptic curve scalar point multiplication is presented. To achieve the maximum architectural and timing improvements، the critical path of the Lopez-Dahab scalar point multiplication architecture has been reorganized and reordered such that logic structures are implemented in parallel and operations in the critical path are diverted to noncritical paths. The results show that with G= 41، the proposed design is able to compute GF (2163) elliptic curve scalar multiplication in 11. 92μs with the maximum achievable frequency of 251 MHz on Xilinx Virtex-4 (XC4VLX200)، where G is the digit size of the underlying digit-serial finite field multiplier. The results of synthesis show that in this implementation 19606 slices or 22% of the chip area is occupied.