Design of an analog current-mode time-delay cell

The goal of this research is designing an analog current-mode time-delay cell based on a current-mode first-order all-pass filter with high output impedance. The proposed all-pass filter as a time-delay cell consists of a class AB cascode current mirror and also a differential input voltage current conveyor (DVCC) as an active element employing only two grounded passive components for phase shifting and required time delay. The proposed time-delay cell is capable of working at low-voltage headroom and has high speed operation and a low-power consumption of 1. 39mW. The value of delay can be controlled by both fine-tuning and coarse-tuning. This time-delay cell can generate a delay of 14ns while it is able to reach a minimum delay of 6ns across a 100MHz bandwidth by using fine-tuning and coarse-tuning of the time-delay cell, as well. The proposed cell can be used in the beamforming, radars, and medical engineering. HSPICE simulations are performed based on a 0. 18µm standard CMOS technology.