A Survey on Lightweight Hardware Implementation of AES

Devices such as wireless sensor networks and RFIDs have limited memory, power and energy. They have security requirements so that the usual implementation of cryptographic algorithms is not appropriate for them and leads to high consumption of resources. One solution is designing new lightweight algorithms that have a lower security level than standard algorithms. The second solution is implementing standard algorithms such as AES block cipher as a lightweight algorithm. In this type of implementation, some techniques such as resource sharing, S-box implementation with combinational circuits, mapping computations finite fields from one base to another base and on the fly computation are used. In this paper, the most important lightweight implementations of AES are evaluated. The criteria considered for this evaluation include gate count, the number of clocks required for an encryption/decryption operation, throughput, power, energy and the combination of themes. Studies show that we can use standard encryption algorithms in applications with limited area between 2000-3000 GE and a small amount of energy, for example a few PJ. Some of these successes are achieved due to advancements in CMOS circuit technology and some others are the result of designing suitable hardware architecture, exact scheduling of cryptographic operations and efficient use of resources.