Implementation a tracker hardware block of GPS receivers on FPGA and failure test

In GPS receivers, due to the structure of the transmitted signal and the influence of physical factors on it, which greatly reduces the received signal power, different blocks are used to extract and retrieve satellite data. The first two blocks are called the acquisition block and the tracking block, respectively. The acquisition block operates to simplify the estimation of Doppler frequency and the code phase, and the tracking block performs the tracking of the satellite signal to extract the navigation data. Locked the PLL and DLL loops of this block on the received signal under critical conditions such as weak signal, accelerated movement, etc. is very important. Therefore, in cases where the loops open and lose the Doppler frequency and phase code of the received signal, depending on the capabilities embedded in the block, the duration of the loops being re-closed is one of the special privileges for this block. This paper deals with hardware implementation of FPGA-based optimized tracking block and evaluates the speed of closing the loops in the block and following the signal with the practical implementation of the hardware.