CMOS Image Sensor with 10-Bit Two-Stage Column-Parallel Data Converter

In this paper, an image sensor is introduced which can take photos at high-speed. For this purpose, a pixel readout circuit has been introduced. So that with the same power consumption of the conventional source follower circuit, linearity and accuracy are improved 14dB and 16%, respectively. Total input referred noise of the pixel readout circuit in the band width of 1hz-1GHz is 0.7mv and power consumption without bias circuit is 16.9µw. The proposed image sensor is designed based on the column- parallel architecture, and a new structure has been introduced to convert pixel analog signals to digital, which can convert pixels signals to 10 bits digital data in two consecutive phases. This method has led to 16 times increase in sampling rate without significantly increasing power consumption compared to a conventional single-slope ADC. All circuits are designed in TSMC 0.18µm CMOS technology and implemented by Cadence software and simulated by the Spectre circuit simulator.