An Improved Standard Cell Placement Methodology using Hybrid Analytic and Heuristic Techniques

In recent years, size of VLSI circuits is dramatically grown and layout generation of current circuits has become a dominant task in design flow. Standard cell placement is an effective stage of physical design and quality of placement affects directly on the performance, power consumption and signal immunity of design. Placement can be performed analytically or heuristically. Analytical placers generate optimal or near-optimal solution but they are not usable for large circuits due to large computation time. In contrast, Heuristic placers can be used to place large circuits with more poor quality rather than analytical ones. In this paper, a hybrid analytical and heuristic approach for standard-cell placement is proposed. In this approach, cell rows are arranged heuristically but the location of cells inside each row are determined analytically. Experimental results show that general metric of placement (total wire length) is improved by 28.6% and this improvement will be more considerable for more large circuits. However, total wire length reduction is gained with a little computation overhead (about 0.01%).