Design of 4 Transistors and 1 Memristor Hybrid Nonvolatile Memory Cell with Low Power, High Speed, and High Density

Memristor is the fourth fundamental element after resistor, capacitor, and inductor. Memristor can become an essential element of SRAM and DRAM caches because of its zero power consumption in data storage and non-volatile state. It can effectively improve the efficiency, speed, and power consumption of circuits. In this paper, we propose a 4T1M memory cell reducing the cell area by maintaining the maximum properties of 6T1M. To simulate the proposed memory cell, the length of the memristors is 10 nm, and the resistance of their on and off states is selected as 1 kΩ and 200 kΩ, respectively. Also, the cell MOS transistors are simulated by the 32 nm HP CMOS PTM model. Simulations in H-Spice software, at 0.9 V power supply, have been conducted to compare the proposed cell characteristics with two conventional six-transistor (6T) and six-transistor one-memristor (6T1M) cells. The results show that using a memristor in a memory cell causes zero power consumption during data storage for a long time and reduces the occupied area by 36.7% compared to the 6T1M cell. The speed of writing “1” data on the proposed cell is only 30 ps, which shows a 3-fold improvement compared to the 6T1M cell, but no significant change is observed when writing “0” data. The static power of the proposed cell is 133 times less than that of a six-transistor cell, and its dynamic power is about the same as the 6T1M cell, but it consumes 60 times less energy than a six-transistor cell.