Low Power Rail-to-Rail Class AB CMOS Operational Amplifier Using Translinear Loop

In this paper the analysis and design of an operational amplifier is presented. This amplifier can follow the input signal from ground to supply voltage at its input and output. Based on the level of the input common mode voltage, one of two pMOS and nMOS differential pairs are selected to amplify the input signal. This causes the amplifier performance is independent of the drain current relationship of the input differential pairs transistors. Both static and dynamic currents of the class AB output stage are provided by two translinear loops with minimum sensitivity to process, temperature and supply voltage variations. The simulation results, in a 0.18  CMOS technology, show that the amplifier in nominal condition, has about 80 dB dc voltage gain, 51 MHz unity gain bandwidth and 63  phase margin while its static power consumption is almost 1 mW. For input common mode voltage changes between ground to the supply voltage, the maximum relative variations of the input differential pairs transconductances, amplifier’s dc voltage gain, phase margin and unity gain bandwidth are , ,  and , respectively. This amplifier as a buffer can drive a load consisting of parallel connection of a resistor  and a capacitor 20 pF.