Proposing Very Low Power Three-Valued Flip-Flops by Using CNTFET Transistors
The scaling limitations of Complementary Metal-Oxide-Semiconductor (CMOS) transistors to achieve better performance have led to the attention of other structures to improve circuit performance. One of these structures is multi-valued circuits. In this paper, we will first study Carbon Nanotube Transistors (CNT). CNT transistors offer a viable means to implement multi-valued logic due to their variable and controllable threshold voltage. Subsequently, we delve into the realm of three-valued flip-flop circuits, which find extensive utility in digital electronics. Leveraging the insights gained from our analysis, we propose a novel D-type flip-flop structure. The presented structure boasts a remarkably low power consumption, showcasing a reduction exceeding 61% compared to other existing structures. Furthermore, the proposed circuit incorporates a reduced number of transistors, resulting in a reduced footprint. Importantly, this circuit exhibits negligible static power consumption in generating intermediate values, rendering it robust against process variations. Overall, the proposed circuits demonstrate a 29.7% increase in delay compared to the compared structures. However, they showcase a 96.1% reduction in power-delay product (PDP) compared to the other structures. The number of transistors is also 8.3% less than other structures. Additionally, their figure of merits (FOM) are 19.7% better than the best-compared circuit, underscoring its advantages in power efficiency, chip area, and performance.
پرداخت حق اشتراک به معنای پذیرش "شرایط خدمات" پایگاه مگیران از سوی شماست.
اگر عضو مگیران هستید:
اگر مقاله ای از شما در مگیران نمایه شده، برای استفاده از اعتبار اهدایی سامانه نویسندگان با ایمیل منتشرشده ثبت نام کنید. ثبت نام
- حق عضویت دریافتی صرف حمایت از نشریات عضو و نگهداری، تکمیل و توسعه مگیران میشود.
- پرداخت حق اشتراک و دانلود مقالات اجازه بازنشر آن در سایر رسانههای چاپی و دیجیتال را به کاربر نمیدهد.