Low-Power Adder Design for Nano-Scale CMOS

Author(s):

S. R. Talebiyan , S. Hosseini , Khayat

Message:
Abstract:
A fast low-power 1-bit full adder circuit suitable for nano-scale CMOS implementation is presented. Out of the three modules in a common full-adder circuit, we have replaced one with a new design, and optimized another one, all with the goal to reduce the static power consumption. The design has been simulated and evaluated using the 65 nm PTM models.
Language:
English
Published:
Iranian Journal of Electrical and Electronic Engineering, Volume:5 Issue: 3, Sep 2009
Page:
180
https://magiran.com/p686826