We have designed and simulated a 10-nanometer regime gate High Electron Mobility Transistor (HEMT) with an undoped region (UR) under the gate with high k dielectric as hafnium oxide (HfO2). The thickness of metal gate(G) and undoped regions are equal but length of channel(C) is not equivalent. The proposed Undoped under the gate dielectric High Electron Mobility Transistor reduces the maximum electric field(V) in the channel region and increases the drain current significantly. The High-K dielectric High Electron Mobility Transistor structure obtained a saturated Ion current of 60% higher than the conventional structure. For High critical Power and High-frequency Power transmission Amplifiers utilizes the AlGaN/GaN/SiC-based High Electron Mobility Transistor with an undoped region under the gate with High-K Hafnium oxide. The Proposed advanced High Electron Mobility Transistor Produces a higher Drain current (Id), 54% high transconductance (Gm) with Low On-Resistance (Ron), and High conductivity in comparison to typical High Electron Mobility Transistor. In Addition to these improved characteristics, the Electric field along the Y direction is also observed. The proposed structure formed by Low-k Dielectric materials in the process of Silicon Dioxide(SiO2) and High-k dielectric being Titanium Dioxide (TiO2) and Hafnium Oxide (HfO2) created more opportunities in Power electronics and radio frequency operations.

In this paper, the performance of an optical modulator based on indium tin oxide is investigated at telecommunication wavelength for different accumulation thickness. The plan of metal-oxide-semiconductor is utilized to change the carrier concentration at indium tin oxide-hafnium oxide interface. An optical mode solver based finite element method has been used to calculate the basic parameters such as the insertion loss and extinction ratio. A typical model is presented for carrier concentration modeling of indium tin oxide. The simulation result shows a peak in insertion loss plot with value of 8.4 dB/μm. Also, the variation of ITO and HfO2 thicknesses have been investigated. The results show that by increasing the thicknesses, insertion loss and extinction ratio decrease. Furthermore, the effect of accumulation layer thickness of indium tin oxide is investigated on modulator performance.

Two-dimensional analytical modelling of Dual Material Gate Tunnel Field Effect Transistor with change in variation of gate oxide thickness (DMG-UOX-TFET) is proposed in this work. This proposed device employs dielectric materials such as hafnium oxide and silicon dioxide, with distinct oxide thicknesses. This device was invented using a technology-aided computer design tool in 10 nm (0.01 µm) technology. This work investigates the impact of gate oxide thickness on the electrical characteristics of the proposed device, with a particular focus on drain current variation. The extensive simulations and key performance parameters of the proposed device were analyzed regarding gate oxide thickness. The various gate oxide thicknesses and their effects on the device subthreshold slope, On- current, Off- current, and on-off-current ratio were analyzed. The proposed device incorporates n-type operations within the gate overlap region, effectively mitigating the corner effect and the detrimental band-to-band tunneling that can degrade the on/off ratio. Through careful optimization of the doping concentration in the gate overlap region, achieved a remarkable ∼4.8 time enhancement in the on-current, while simultaneously reducing the average subthreshold swing from 91.3 mV/dec to 52.8 mV/dec.

In this study, the effect of annealing treatment on microstructure and mechanical properties of Nb-10Hf-1Ti wt.% produced by Spark Plasma Sintering (SPS) was investigated. Scanning electron microscope (SEM), optical microscopy, X-ray diffraction analysis, hardness, and uniaxial tension test were used. Annealing treatment was carried out in a vacuum of 10-3 Pa at 1150 °C for 1, 3, 5, and 7 hours and in an argon atmosphere at 1350 °C for 5 hours. Internal oxidation and subsequent hafnium oxide formation causes the hardening of the C103 alloy and drastically increases hardness and tensile strength. Although HfO2 particles formed in the grain boundary cause brittleness and cleavage fracture of samples. Volume fraction, particle size, and mean interparticle spacing of oxides significantly change by annealing and subsequently the mechanical properties are affected. The SPSed sample at 1500 ℃ is softened by annealing at 1150 ℃ for 5 hours and its hardness and yield strength are reduced from 303 Hv to 230 Hv and 538 MPa to 490 MPa respectively. While annealing at 1350 ℃for 5 hours increases hardness and yield strength increases to 343 Hv and 581 MPa.

The devices with additional gates like Fin Field effect transistor (FinFET) provide higher control on subthreshold parameters and are favorable for Ultra large-scale integration. Also, these structures provide high control on current through the channel and with minimum leakage. In this paper we designed a FinFET with high-K gate dielectric material i.e Hafnium oxide as gate oxide. A comparison of similar sized transistor with Air and Silicon dioxide as gate material is performed. The comparison is mainly in terms of performance parameters like transconductance, subthreshold slope, and drain current characteristics. There is an increase in ON current on using a high-K dielectric material and subsequently an improvement in other parameters like subthreshold slope, transconductance and intrinsic gain.

In this work, a Symmetrical Dual Gate Tunnel Field Effect Transistor (SDGTFET) is proposed with gate dielectric materials in 10nm technology. The electrical performance parameters of this proposed device are investigated using technology computer aided design (TCAD) simulator. The new SDGTFET employing with high-k dielectric material such as hafnium oxide (HfO2) and interfacial layer (IL). The 2nm HfO2 with 30 dielectric constant is used between the interfacial layer and the metal gate on both sides of the device. The variation of the drain current with the varying of gate length, effective gate materials and effective oxide layer thickness of the device is evaluated in this work. By optimizing the proposed device with gate dielectric material the on current gets ∼4.2 times enhanced and the averaged subthreshold swing (SSavg) becomes reduced from 90.2 mV/dec to 53.8 mV/dec. Therefore, the SDGTFET structure has better performance than single material and double material TFET and shows a lower ambipolar current and a better on current to off current ratio.

This paper investigates the electrical behavior and performance of a  Dual Metal Gate Overlap on  Drain Side Tunnel Field Effect Transistor with Spacer (DMG-ODS-TFET) in 10 nanometer technology. In this design, the utilization of two different metals to create the gate effectively maintains electrostatics and minimizes gate leakage current. This structure is formed by silicon dioxide and hafnium oxide as dielectric materials. The drain current characteristics such as subthreshold swing, on-state current, off-state leakage current, and transconductance are calculated for the proposed device using the available two-dimensional numerical device simulator silvaco tool. The characteristics of the proposed device vary with changes in channel length, doping concentrations of the drain and source, and the thickness of the oxide layer. This structure shows a lower off current, and better on-to-off current ratio with improved drain current. Consequently, the proposed design effectively balances gate control and leakage current, resulting in superior to conventional and dual metal gate devices. Based on improved performance parameters, this proposed structure is suitable for high-frequency applications.

A High-K Dielectric Dual Metal Gate FinFET (DMG-FinFET) is proposed in this work to improve the drain current and electrical characteristics of the device. The proposed device employing dielectric materials such as Silicon dioxide, Hafnium oxide and Titanium oxide and investigated in 10 nm technology. The architecture represents a critical advancement in transistor design, addressing challenges posed by traditional high-K gate dielectric materials being HfO2 and TiO2. This work employs a comprehensive approach, incorporating simulation techniques to evaluate the performance metrics of DMG FinFET. This investigation encompasses key aspects being transistor characteristics, power consumption, and reliability. This high-k dielectric (HfO2) Dual material Gate –FinFET device achieving improved performance parameters such as Ion= 32.12 mA, Ioff= 33 μA, Gm(max) = 0.045 S, Gds(max) = 0.024 S and Ron(max) = 32.87 kΩ. Therefore this work is suitable for designing high performance devices with high-k dielectric materials being HfO2 and TiO2.  The impact of dual metal gate materials on Ion, Ioff, Gm (max), Gds(max) and Ron(max) is calculated and improved 64% compared to conventional device.

A Hetero Dielectric Tunnel field effect transistor with the spacer on both sides of the gate is proposed in this paper. The performance and characteristics of Hetero Dielectric Tunnel field effect transistor using the ATLAS Technology Computer-Aided Design in 5nm regime were analyzed. The band-to-band tunneling leakage current will be reduced by introducing heterojunction and hetero dielectric spacer material in the proposed structure. In Hetero Dielectric Tunnel field effect transistor, double metal gate and high-k dielectric spacer improves high on the current and subthreshold swing. The high-k dielectric Hafnium oxide spacer is placed on both sides of the source and drains to import the tunneling mechanism. The proposed device in the 5nm node has improved DC characteristics such as a High ON-state current of 1.68 x 10-5 Amp & OFF-state Current reduced from 7. 83x 10-11 Amp to 5.13 x 10-12 Amp and ION / IOFF ratio has increased from 3.22 x 105 to 3.27 x 10  compared to conventional dual gate Tunnel field effect transistor. Therefore, this device is suitable for low power applications

This paper presents a novel design and analysis of a Low-k Source side Asymmetrical Spacer Halo doped Nanowire TFET. The utilization of high-k hafnium oxide spacer materials in TFET enhance electrostatic control and minimize short-channel effects in nanoscale devices. However, the performance of dynamic circuits suffers with higher fringe capacitance brought on by high-k spacers. Our method focuses on reducing gate capacitance by optimistic utilization of high-k spacer material. The proposed device is constructed in SILVACO TCAD software and results states that the use of Low-k material as silicon dioxide at the Source-side spacer in halo-doped nanowire TFET design results in significantly reduced gate-capacitance and intrinsic-delay. For this proposed TFET device, the circuit performance of advanced nanowire structure can improve drain current characteristics and analog characteristice.  The proposed device exhibits better performance as compared to other spacer engineering devices. As a consequence, the suggested device appears as a strong suitable device for low power digital applications.