Iranian Journal of Electrical and Electronic Engineering
Volume:15 Issue: 4, Dec 2019

The Functional Electrical Stimulator design using monophasic spike-exponential waveform was proposed and described in this study. The monophasic square waveform has benefit in generating an action potential, but it could cause side effects such as toxic caused by the electrode polarization. The square waveform signal which the frequency and pulse width could be modulated was manipulated to be the monophasic spike-exponential waveform. Transformer OT240 was applied at the end of the FES system part and functioned as a voltage amplifier and DC signal isolator. On every frequency range between 5–100 Hz, the 16 peak voltage stages with the lower limit of 45 Volt and an upper limit of 400 Volt was arranged to obtain VRMS value in each stage. Characterization result shows that the produced waveform was monophasic spike-exponential with the narrow pulse width (t1/2 = 7 µs) and VRMS in the maximum frequency and peak voltage was 8.99 Volt. This study showed that the designed FES had high VP and low VRMS, thus, it could be concluded that this FES system design could be a candidate for its application.

Design of Global Positioning System (GPS) receiver with a low noise amplifier (LNA) in the front end remains a major design requirement for the success of modern day navigation and communication system. Any LNA is expected to meet the requirements like its ability to add the least amount of noise while providing sufficient gain, perfect input and output matching, and high linearity. However, most of the reported designs of LNAs present the need for striking a trade-off between these design parameters in order to obtain the desired performance for a particular RF receiver. This paper presents high gain (21dB), high input matched (-29dB), high reverse isolation (-41dB) and low noise figure (< 2dB) narrowband LNA for extremely low power level GPS L1 band signals broadcasting at 1.57GHz with a channel bandwidth of 10MHz. Inductive source degeneration topology is employed for the design and all the matching inductors in the circuit are used with fixed quality factor (Q) to model the losses for better tuning and matching. The design is carried out on Cadence Virtuoso Tool version IC6.1.6 and Spectre version MMSIM13.1 at 0.18µm technology node using a generic process development kit. Detailed mathematical analysis of the design is done and all the DC parameters like values of transconductance, gate source capacitance, drain source voltage, drain current, etc. are reported. Graphical analysis using Smith chart is carried out to present the results and to bring forth the trade-offs involved in the design. LNA draws 5mA current from 1.2V supply voltage and offers good linearity that is sufficient for GPS application and is measured by input intercept point 3 (IIP3 < ‑4dBm).

In this paper, a chattering-free sliding-mode control is mainly proposed in a second-order discrete-time system. For achieving this purpose, firstly, a suitable control law would be derived by using the discrete-time Lyapunov stability theory and the sliding-mode concept. Then the input constraint is taken into account as a saturation function in the proposed control law. In order to guarantee the closed-loop system stability, a sufficient stability condition would be addressed in the presence of unstructured uncertainties. Hence the states of the discrete-time system are moved to a predefined sliding surface in a finite sampling time. Then the system states are asymptotically converged to the origin through the sliding line. The suggested SMC is successfully applied in two discrete-time systems (i.e. regulation and tracking problems). The effectiveness of the proposed method will be verified via numerical examples.

An efficient Lookup Table (LUT) design for memory-based multiplier is proposed.  This multiplier can be preferred in DSP computation where one of the inputs, which is filter coefficient to the multiplier, is fixed. In this design, all possible product terms of input multiplicand with the fixed coefficient are stored directly in memory. In contrast to an earlier proposition Odd Multiple Storage (OMS), we have proposed utilizing Even Multiple Storage (EMS) scheme for memory-based multiplication and by doing so we are able to achieve a less complex and high-speed design. Because of the very simpler control circuit used in our design, to extract the odd multiples of the product term, we are also able to achieve a significant reduction in path delay and area complexity. For validation, the proposed design of the multiplier is coded in VHDL, simulated and synthesized using Xilinx tool and then implemented in Virtex 7 XC7vx330tffg1157 FPGA. Various key performance metrics like number of slices, number of slice LUT’s and maximum combinational path delay is estimated for different input word length. Also, the performance metrics are compared with the existing OMS design. It is found that the proposed EMS design occupies nearly 62% less area in terms of number of slices as compared to the OMS design and the maximum path delay is decreased by 77% for a 64-bit input. Further, the proposed multipliers are used in Transposed FIR filter and its performance is compared with the OMS multiplier based filter for various filter orders and various input lengths.

In this work, the design and analysis of new Level Shifter with Gate Driver for Li-Ion battery charger is proposed for high speed and low area in 180nm CMOS technology. The new proposed level shifter is used to raise the voltage level and significantly reduces transfer delay 1.3ns (transfer delay of conventional level shifter) to 0.15ns with the same input signal. Also, the level shifter with gate driver achieves a propagation delay of less than 0.25ns and the total area is only 0.05mm2. The proposed level shifter with gate driver was designed, simulated and layouted in Cadence using TSMC 180nm CMOS technology.

Accurate delay calculation of circuit gates is very important in timing analysis of digital circuits. Waveform shapes on the input ports of logic gates should be considered, in the characterization phase of delay calculation, to obtain accurate gate delay values. Glitches and their temporal effect on circuit gate delays should be taken into account for this purpose. However, the explosive number of combinations of waveform shapes, which can be applied to the input ports of logic gates, causes existing lookup-based methods to have huge space requirements. In this article, instead of considering all possible combinations of waveform shapes in the characterization phase of delay calculation process, the least number of combinations, which are dominant in determining the waveform shape of gate output, is presented. Multivariate Polynomial Regression (MPR) method is used to further reduce the required memory space. Exploration of the possible MPR analyses is performed to find the best regression case with proper memory space reduction and precision. Attained results show a 1.013E6 times reduction in storage space required for storing parameters utilized in extraction of output waveform characteristics in comparison to a state of the artwork, accompanied by acceptable precision.

This work presents a dual-junction, single-photon avalanche diode (SPAD) with electrical μ-lens designed and simulated in 90 nm standard complementary metal oxide semiconductor (CMOS) technology. The evaluated structure can collect the photons impinging beneath the pixel guard ring, as well as the pixel active area. The fill factor of the SPAD increases from 12.5% to 42% in comparison with similar works on the same technology, according to new charge collections. Although the designed SPAD suffers from high dark count rate (DCR of 300kHz at 0.17V excess bias at room temperature) due to high amount of tunneling which was predicted in previous similar works, it still can be used in different applications such as random number generators and charged particle positioning pixels.​

A model of a low noise high quantum efficiency n+np Germanium Photodiode utilizing ion implantation technique and subsequent drive-in diffusion in the n layer is presented. Numerical analysis is used to study the influence of junction depth and bulk concentration on the electric field profile and quantum efficiency. The performance of the device is theoretically treated especially at the wave-length region 1.55μm where the Silica optical fiber has minimum attenuation loss. It has been found that at this wave-length and for the optimum device design the quantum efficiency approaches about 90%.

This paper presents the three topologies of three-phase four-wire DSTATCOM for reduction of harmonics, reactive power compensation, increasing power factor, which occur due to a nonlinear load, environment problem and polluted grid. The performances of the above topologies have been compared for the magnitude of source current, power factor improvement, DC-link voltage regulation, and total harmonic distortion. This paper presents a novel work for the new young scientist /industrialist who working in the improvement of power quality in the grid. This paper helps to provide the application, designing constraints of shunt active filter in many fields. The First topology which is used in this paper is the three-phase four-wire four-pole voltage source converter based DSTATCOM. The second is the three-phase four-wire with three-leg voltage source converter based DSTATCOM with T-connected transformer and the third topology is the three H-bridge voltage source converter based DSTATCOM. The T-connected transformer in the second topology has been used to reduce the rating for voltage source converter. Synchronous reference frame theory based controller has been proposed to the generation of the reference current. Reference current generated from the synchronous frame theory is processed to hysteresis current controller loop which produces switching pulses for VSC based DSTATCOM. All these topologies have been implemented in MATLAB /Simulink platform by using different types of loading conditions such as resistive and power electronics load.​

This paper presents a novel impedance-based approach for out-of-step (OOS) protection of a synchronous generator. The most popular and commonly used approaches for detecting OOS conditions are based on the measurement of positive sequence impedance at relay location. However, FACTS devices change the measured impedance value and thus disrupt the performance of impedance-based relay function. In this paper, the performance of synchronous generator OOS protection function connected to the transmission line in the presence of a static synchronous compensator (STATCOM) is investigated. Moreover, an analytical adaptive approach is used to eliminate the effect of STATCOM. This approach requires only the remote bus voltage and current phasors to be sent to the relay location via a communication channel. Simulation results show that STATCOM changes impedance trajectory and causes the incorrect operation of OOS relay. Furthermore, the proposed approach corrects the relay mal-operation and improves the accuracy of OOS impedance-based function when the STATCOM is used in the system.​

In this paper, a new method for modelling and estimation of reliability parameters of power transformer components in distribution and transmission voltage levels for preventive-corrective maintenance schedule of transformers is proposed. In this method, with optimal estimation of Weibull distribution parameters using least squares method and input data uncertainty reduction, failure rate and probable distributions of power transformers’ components as the key parameters of equipment reliability is estimated. Then by using the results of this modelling, a maintenance schedule for evaluation the effect of maintenance on reliability of this equipment is presented. Simulation results using real failure data of 196 power transformers on 33 to 230kV voltage levels show that applying the proposed method in addition to uncertainty reduction of raw input data and better estimation of equipment reliability, improve decision making regarding maintenance schedule of power transformers.

In this paper, a new design of permanent magnet linear synchronous motor (PMLSM) for electromagnetic launcher system (EMLs) has been investigated in terms of the requisite amount of average launching thrust force and thrust force ripple minimization through finite element method. EMLs are a kind of technology used to develop thrust force and launch heavy loads with different applications including military, aerospace, and civil applications. A linear motor as a major part of the system plays a substantial role in this application providing sufficient load launch force. Cogging force and its mitigation techniques are principle challenges in linear motor operation leading to thrust ripples and detrimental effects on positioning precision and dynamic performance of the moving part. In the proposed design, some modifications have been made in the conventional PMLSM structure. Semi-closed slot construction is used for the primary and the pole shoes width has been changed to access minimum thrust ripple value. In order to attain further optimization in PMLSM’s thrust ripple profile, some other modifications have been considered in PM’s shape as arc-shaped magnetic poles. The latter assists to enforce air gap flux density distribution as sinusoidal as possible, and makes further ripple reduction. The results exhibit that the proposed structure has low weight and it is more economical compared to conventional PMLSM with rectangular shape magnet. In addition, the Average thrust force and ripple are improved providing suitable thrust force for throwing the load.

In this paper, the new approach for the transmission reliability cost allocation (TRCA) problem is proposed. In the conventional TRCA problem, for calculating the contribution of each user (generators & loads or contracts) in the reliability margin of each transmission line, the outage analysis is performed for all system contingencies. It is obvious that this analysis is very time-consuming for large power systems. This paper suggests that this calculation should be done only for major contingencies. To do this, at first, the contingency filtering technique (CFT) is introduced based on the new economic indices that quantify the severity of each contingency to determine the critical contingencies. Then the results of contingency filtering are used in the TRCA problem. The simulation results are reported for the IEEE 118-bus test system. The obtained results show that by application of CFT in TRCA problem, the simulation time is greatly reduced, but the percentage of error remains within an acceptable limit.​