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The essential reason for implementing multilevel processing systems is to reduce the number of semiconductor elements and hence the complexity of system. Multilevel processing systems are realized much easier by carbon nanotube field effect transistors (CNTFET) than MOSFET transistors due to the CNTFET transistors' adjustable threshold voltage capabilities. In this paper, an efficient quaternary full-adder based on CNTFET technology is presented which consists of two half adder blocks, a quaternary decoder and a carry generator circuit. In the proposed architecture, the base-two and base-four circuit design techniques are combined to take the full advantages of both techniques namely simple implementation and low chip area occupation of the entire proposed quaternary full-adder. The proposed structure is evaluated using the Stanford 32nm CNTFET library in HSPICE software. The simulation results for the proposed full-adder structure utilizing a supply voltage of 0.9 volts, reveals the power consumption, propagation delay and energy index equal to 2.67 μW, 40 ps, and 10.68 aJ, respectively.

The increasing growth of processing data size in digital systems has increased the number of connections between processing systems, which requires a lot of space to establish communication with other processing systems. The design and implementation of multi value level processing systems reduce the size of processing data. On the other hand, the important issue in the implementation of multi-level processing systems is problems and complications of design. The use of substitute transistors such as nano-carbon tube field effect transistors instead of metal oxide semiconductor field effect transistors while reducing design problems in nano dimensions is functionally more suitable than metal oxide semiconductor field effect transistors. In this article, a report on the implementation of a multi inputs full ternary comparator based on carbon nanotube field effect transistor technology is presented. The implementation report of the one digit and two-digit ternary comparator at the transistor level has been done in this article, and the implementation method of the multi-input ternary comparator has also been presented. The simulation results in the HSPICE software environment show that the power consumption of the proposed comparator is 0.55 µW and the propagation delay time is 70 ps. In addition, the proposed comparator has been implemented based on 32 nm carbon nanotube field effect transistors technology.

This paper presents a cascaded 2-2 reconfigurable sigma-delta modulator that can handle GSM and WCDMA standards. In GSM mode, only the first stage (2nd order Σ-Δ ADC) is turned on to achieve 83dB dynamic range with oversampling ratio of 160 for a bandwidth of 200 KHz ; in WCDMA mode a 2-2 cascaded structure (4th order) is turned on with 1-bit in both stage to achieve 65 dB dynamic range with oversampling ratio of 16 for a bandwidth of 2 MHz .The results show that power consumption of proposed modulator is lower than other counterparts. Modulator are simulated by Cadence software utilizing 180 nm TSMC technology and operates at 1.8 supply voltage.

In this paper, the new structure N×M (N-Ternary inputs and M-Binary outputs) Ternary to Binary Converter based on Carbone Nanao Tube Field Effect Transistor is presented. The Carbone Nanao Tube Field Effect Transistor (CNTFET) has especial properties as controlled threshold voltage. The aforementioned advantages related to the multi-level (more specifically Ternary) circuits and systems based on CNTFET technology have encouraged researchers to put more effort on their design and realization in recent years. The Encoder (one input- five outputs), 3×1 multiplexer (one input – one selector-three outputs) and especial Adder blocks (Full Adder and Half Adder) are base blocks that are implemented by transistor level using especial properties of CNTFET transistor. In general, to implement a N-input ternary-to-binary converter, the number of inputs can be divided into two small converters, and also a ternary-to-binary converter can be designed for each input. In this paper, 2×4, 3×5, 4×7 and 5×8 Ternary to Binary converters are designed and simulated by Hospice and 32 nano meter technology. The result of simulation is shown that 5×8 Ternary to Binary converter has 1.89 µW DC-Power and 52 ps propagation delay. The proposed 5×8 TTBC converter is implemented by 365 CNTFET transistors and divided two ternary to binary converters.

Utilizing multiple logic instead of binary logic levels makes the same system to be realized with reduced number of internal connections and wiring, occupying smaller chip area while achieving higher operational speed. Due to the unique features nanotubes carbon tubes field effect transistors, as well as the possibility of designing different threshold voltages for transistors, designing multi-level logic systems is much simpler and less costly. Therefore, considering that the existing processing systems work on a dual basis, the design of binary to ternary converters and vice versa is very important and basic processing systems. In spite of all advantages mentioned, the multilevel logic systems relay on voltage dividing mechanism to provide suitable mid-voltage outputs. This, however, requires a direct current flow from supply voltage to the ground making the structure power hungry. Eliminating the mid-voltage outputs can help the structure to resemble binary design approach and be more power efficient as discussed in this paper. In this paper, pseudo ternary addition blocks, namely a half-adder, a full-adder block are designed and implemented based on CNTFET which try to eliminate '1' output for mid-stages wherever possible. The proposed adders are implemented, simulated and verified in HSPICE software using 32nm CNTFET technology. The simulation results reveal the proposed pseudo ternary full-adder block consumes just 1.037 μW power and has the propagation delay of 290 ps.

Performance of the current steering digital to analog converters are limited by transistors channel width and length mismatches and their Threshold and Early voltage variations due to fabrication process errors. Although there are several ways to reduce errors due to element mismatches, however these errors cannot be completely eliminated. In this paper, Distributed MOS Transistor Technique is utilized which facilitates Dynamic Element Matching implementation capability in Binary Digital to Analog Converter. The proposed technique reduces the errors due to element mismatches and also load voltage variations needless of high power consumption and complex circuitry. This technique operates based on random selection of unit current blocks among specific number of available current units. To make the generated code as random as possible, a random code generator, full adder and 4*16 decoder have been used. This technique is realized in a 10-bit digital to analog converter with 180 nm CMOS technology. The LSB current is 500nA and supply voltage is 1.8v and the power consumption of this converter is 14.6 mW and SFDR of DAC is achieved 60.27 dB based on simulation result with Cadence Spectre software.

This paper presents an optimized multi-digit Ternary to Binary converter based on nano-carbone tubes field-effect transistors. By modifying a part of the circuit structure of the ternary-to-binary converter, the efficiency of the system has increased. Due to the unique features nanotubes carbon tubes feild effect transistors, as well as the possibility of designing different threshold voltages for transistors, designing multi-level logic systems is much simpler and less costly. Therefore, considering that the existing processing systems work on a dual basis, the design of binary to bernary converters and vice versa is very important and basic processing systems. Therefore, considering that the existing processing systems work on a binary, the design of binary to turner and turner to binary converters is very important and fundamental in processing systems. The circuit modification has reduced chip occupancy, reduced power consumption, and reduced circuit latency. The proper and optimal performance of the proposed converter have been confirmed by simulation by HSPICE software based on 32 nm CNTFET transistor. The simulation results show that the optimal terbnary to binary converter has a power consumption of 0.665 μW and a propagation delay of 27.3 ps. These results show that overall PDP index has improved by 14.4%.

The multipliers are important blocks that used in digital processing modern systems. So, design of the efficient multiplier is important advantage for digitally computational system. In some processing fields as the signal processing, the specified level of the error is acceptable, so used of accurate multiplier in the all of the processing fields is not essential. One of the important blocks of the multiplier is the compressor that is used in stage of the partial multiplication for decreasing operations. In this paper, new design of the 5:3 and 15:4 approximate compressors are proposed, the power consumption, propagation delay and error distance of proposed compressors in the comparison others have proper operating, with used of the proposed approximate compressors designed the approximate 16*16-bit multiplier. The overall of the proposed approximate multiplier is simulated and implemented by 180 nm CMOS technology and 1.8 V power supply by the Cadence tools. The result of simulation is shown that propagation delay proposed 5:3 compressors is 0.76 ns and power consumption is 0.935 μW with ±2 error distance. And also, the proposed 15:4 compressor has 1.12 ns propagation delay, 4.75 μW power consumption.

In this paper, the structure of a 16-by-16 unsigned hybrid (serial-parallel) multiplier has been proposed. Parallel multipliers, incomparison with serial multipliers,have higher speed and higher power consumption. In hybrid structures, to reduce power and increase speed,both serial and parallel techniques are used. The proposed structure improves propagation delay and reduces power consumption using pipeline and retime techniques. Simulation results show that it has 5.7 ns propagation delayand 2.65 mW power consumption. The figure of merit for energy consumption is 15.2 PJ. The proposed multiplier has been designed using 0.18 μm TSMC process at 1.8 V supply and simulated using Cadence tools. The layoutof the multiplier occupies 52414 μm2.

In this paper, dynamic comparators structure, by employing two methods for power consumption reduction with applications in low-power high-speed analog-to-digital converters, have been presented. The proposed comparators have low consumption thanks to power reduction methods. They have the ability for adjusting the offset. The comparators consume 14.3 and 24 μW at 100 MHz, which is equal to 3.7 and 11.8 fJ. The comparators are designed and simulated in 180 nm CMOS. Layouts occupy 210 and 240 μm2, respectively.

Design and implementation of an FPGA based system is illustrated in this paper. This Device is utilized to control temperature and humidity sensitive environments with the aid of humidifier and fan devices. In situ control of humidity and temperature values by incorporated sensors and sending real time instructions to control these amounts is this device’s principle of operation. The capability of the fabricated device to send data via Bluetooth which meanwhile uses an special protocol to encrypt data transmit as well as incorporated error detection and correction protocol makes the device capable to be utilized in places demand ultrahigh immune approach. The Device is also capable to communicate with the computer and store the obtained information. To evaluate the performance of the proposed circuit the system is first simulated in Matlab and then it is implemented in logical gate level at Xilinx ISE environment and finally is practically implemented by Xilinx SPARTAN 3 FPGA and its performance is evaluated experimentally.

The current research is studying the role of ownership structure and cash holding on the accepted companie's value in Tehran Stock Exchange. The sample of the research includes 62 corporations within 2008 to 2013.The ownership structure can direct the corporate toward better performance and increasing its value and has remarkable importance for increasing the company's success and society's economics. According to the results based on variance analysis, there is positive and significant relationship between ownership structure and corporate value while there are not significant relationships between other independent variables such as the size of the board of directors, power of the board of directors and cash holding with dependent variable (corporate value). Regarding the controlled variables of the research, which are financial leverage, dividend payout ratio, Q Tubin, there is a positive and significant relationship between the corporate value and financial leverage, while the other controlled variables do not have significant relationship with corporate value.