Fault-Tolerant 3-D Network-on-Chip Design using Dynamic Link Sharing

Emerging 3D technology partitions a larger die into smaller parts and then stacks them in a 3D fashion. This technology can lead to a paradigm shift in on-chip communication design providing higher orders of bandwidth and lower latency. However, due to the aggressively scaled transistors in modern technology nodes, the reliability issue has become into a major concern. In this paper,we leverage these ultra-low-latency vertical links to design a fault-tolerant 3D NoC architecture. In this architecture, permanent and intermittent defects on links and crossbars are bypassed by borrowing the idle bandwidth from vertically adjacent links and crossbars. Evaluation results under synthetic and realistic workloads show that the proposed fault-tolerance mechanism offers higher reliability and lower performance loss, when compared with state-of-the-art fault-tolerant 3D NoC designs.