جستجوی مقالات مرتبط با کلیدواژه « full adder » در نشریات گروه « فناوری اطلاعات »

In this paper, all-optical photonic crystal two bit adder based on nonlinear ring resonator is designed. The proposed structures includes threshold detectors and junctions. In our proposed structure, in order to resolve the low transmission problem in input junction, an enhanced junction is cascaded by a threshold detector to implement full adder cells. By cascading two optimized full adder a two bit adder has been designed. Nonlinear rods of the proposed structures are made of Silicon nanocrystal to create the required frequency shift for implementation of the proposed structures. In order to evaluate the performance of the proposed structures, the plane wave expansion and finite difference time domain methods are used. The proposed optimized full adder cell occupy an area about 340 µm2 with maximum power 5 W for switching mechanism. Our simulation results show that the proposed full adder can operate with a bit rate of more than 580 Gbits/s.

In this paper, a full adder cell based on majority function using Carbon-Nanotube Field-Effect Transistor (CNFET) technology is presented. CNFETs possess considerable features that lead to their wide usage in digital circuits design. For the design of the cell input capacitors and inverters are used. These kinds of design method cause a high degree of regularity and simplicity. The proposed design can be used in many applications specifically wherever the low power consumption is the goal. The proposed full adder cell is compared to five full adders in terms of power consumption, speed, and power delay product (PDP). Also in order to evaluate the proposed design, several simulations are performed in different load capacitors, frequencies and temperatures. Simulation results demonstrate the higher efficiency of the proposed full adder cell with respect to other conventional and modern CNFET and MOSFET implementations. All Simulations are performed by using Synopsys HSPICE with 32 nm CMOS and 32 nm CNFET technologies.

The conventional CMOS technology faces different challenges such as fabrication in nanoscale which motivates researchers to find new alternatives to it for future high-performance systems. The quantum-dot cellular automata (QCA) is one of efficient nano-electronics technologies which can provide simple and efficient implementation of digital circuits in nanoscale. Due to the importance of addition in digital processors and embedded systems, there many QCA designs of adders and subtractors during the previous years. However, recently the unified design of adder and subtractor circuits has been considered to achieve overall area and delay reduction for digital computational circuits. In this paper, we present new coplanar design of a unified adder/subtractor unit with the QCA technology. Besides, the proposed single-layer design approach has been used to design separate half adder, half subtractor, half adder and full adder circuits. The comparison of circuit’s parameters of the proposed designs than previous works show the significant improvement in term of area, delay and cell number.

Scaling challenges and limitations of conventional silicon transistors have led the designers to apply novel nano-technologies. One of the most promising and possible nano-technologies is CNT (Carbon Nanotube) based transistors. CNFET have emerged as the more practicable and promising alternative device compared to the other nanotechnologies. This technology has higher efficiency compared to the silicon-based MOSFET and is appropriate for high-frequency applications. Full Adder cell is the essential core and the building block of most arithmetic circuits and is placed on most parts of their critical paths .In this paper, power-efficient CNFET (Carbon Nanotube Field Effect Transistor) based Full Adder cell is proposed. This design is simulated in several supply voltages, frequencies and load capacitors using HSPICE circuit simulator. Considerable improvement is achieved in terms of power and PDP (Power-Delay-Product) in comparison with other classical CNFET-based designs, in the literature. Our proposed Full Adder can also drive large load capacitance and works properly in low supply voltages.

Full adder cell is often placed in the critical path of other circuits. Therefore it plays an important role in determining the entire performance of digital system. Moreover, portable electronic systems rely on battery and low-power design is another concern. In conclusion it is a vital task to design high-performance and low-power full adder cells. Since delay opposes against power consumption, we focus on Power-Delay Product (PDP) as a figure of merit. In this paper using carbon nanotube field-effect transistors (CNFETs) a novel low power and low PDP 1-bit full adder cell is proposed. The novel cell is based on capacitive threshold logic (CTL) and to strengthen its internal signals transmission gates (TGs) are applied. Using both CTL and TG techniques lead to achieving low power consumption full adder cell. Intensive simulations with 32nm technology node using Synopsys HSPICE with regard to different power supplies, temperatures, output loads, and operating frequencies are performed. All simulations confirm the superiority of the proposed cell compared to other state-of-the-art cells.