Design of an Ultra High-Speed CMOS D-Latch

In this paper, a current mode D-latch and improvement of its speed and performance are investigated. The primary structure of current mode D-latches was altered frequently. Speed and power consumption are the maintwo factors in designing such circuits. In this work, two ideas are investigated, using an active inductance load in the holding section and utilizing transistor capacitor for coupling the input and eliminating low frequency effects. The active inductor at the output cancels capacitance effects and thus speeds up the response. Accordingly, rise and fall times are reduced significantly. The circuit is implemented by means of 90-nm CMOS transistors and the supply voltage is 1 V. Based on simulation results, in the squared pulse frequency of 10 GHz the delay is 1.11 ps, rise times 3.64 ps, and fall time 3.57 ps. The peak-to-peak differential output sweep voltage is 0.464 V. The static power dissipation of the circuit is 200 μW. Simulation results show that the input signals with up to 40 GHz frequency can be applied to the new presented latch in the cost of only 400 fs peak-to-peak jitter. These characteristics made the circuit suitable for the ultra-high speed communications.