Optimal fast digital error correction method of pipelined analog to digital converter with DLMS algorithm

In this paper, of digital error correction algorithm in of capacitor mismatch error and finite and nonlinear gain of Op-Amp has increased significantly by the use of DLMS, an evolutionary search algorithm. To this end, a 16-bit pipelined analog to digital converter was modeled. The obtained digital model is FIR filter with 16 adjustable weights. To adjust of , was divided into three stages and in each stage, the number of filter weights by DLMS algorithm and totally the error correction algorithm is converged through 3000 repetitions in three stages. The DLMS algorithm was simulated using synthesizable RTL code in Verilog HDL and may be implemented. The division of the error correction algorithm into three stages led to improve the error correction and reduce the power consumption. Moreover, an optimum MDAC circuit has been proposed for designing pipelined converter and based on this circuit the error correction algorithm has been designed.