Design and Implementation of Radar Tester Using SDR

The main application of pulse Doppler radars is to process and calculate target speed and distance.in recent decade’s Radar testers and simulators have been applied to evaluate the efficiency and reliability of this type of radar and to reduce operating costs. The performance of these emulators can include the effects of environmental disturbances, target Properties, and etc. The best way to test the performance of radar systems is to inject signals into different parts of radar.The radar system can be evaluated completely by injecting a coherent RF signal from the antenna. The best way to generate a coherent signal is to use digital radio frequency memory (DRFM) technology. A DRFM consists of five primary section: down converter, analog-to-digital converter (ADC), memory, digital-to-analog converter (DAC), and up converter. Digital memory can be implemented by using the digital equipment and in the others analog parts, for more flexibility SDR (radio-defined software) can be used. At the beginning of this paper, Hardware configuration of the AD9361 (SDR) on the FPGA will be done. Then by using a DRFM feature, a tester will be designed that can test the radar by creation of virtual targets with virtual distance (RGPO/RGPI) and virtual speed (VGPO/VGPI) relative to the radar. This DRFM has 50MHz instantaneous bandwidth and 70 MHz up to 6 GHz working frequency and can detect pulses with 100ns to 0.6ms width and maximum output power 10 dbm finally, by implementing these methods on FPGA, the desired tester structure is obtained.