In this paper the design of a new high-speed current mode BiCMOS logic circuits isproposed. By altering the threshold detector circuit of the conventional current mode logic circuitsand applying the multiple value logic (MVL) approach the number of transistors in basic logicoperators are significantly reduced and hence a reduction of chip area and power dissipation as wellas an increase in speed is achieved. Simulation with HSpice using BSIM 3V3 model and experimental65nm BiCMOS technology were carried out for speed, and power consumption considerations atdifferent supply voltage levels. Finally the performance of the proposed circuit is compared to an 8 bitvoltage mode adder.

ALU is one of the most sensitive units of a processor, which most of the instructions of a processor are executed by this section. In most of the Architecture methods for mitigation of fault such as temporal redundancy, it is necessary to detect the errors first. Hardware overhead of test circuits is one of the most important disadvantages for testing small circuits which makes designers to use unusual methods in the design of small circuits. In this Article, a new implementation method for Berger code has been used to detect the error and compared with the previous method that is based on the Berger code. In the proposed method, the current mode circuits are employed to reduce the cost of the Berger code implementation. This circuit has higher speed and less hardware complexity than conventional implementations of Berger code. According to the result of this article, the Power of current mode Berger has been reduced at a rate of 51%, and the area of current mode Berger has been reduced at a rate of 74.3% and also the total cost of the Berger circuit (Power*Delay*Area) has been reduced at a rate of 91%.

The goal of this research is designing an analog current-mode time-delay cell based on a current-mode first-order all-pass filter with high output impedance. The proposed all-pass filter as a time-delay cell consists of a class AB cascode current mirror and also a differential input voltage current conveyor (DVCC) as an active element employing only two grounded passive components for phase shifting and required time delay. The proposed time-delay cell is capable of working at low-voltage headroom and has high speed operation and a low-power consumption of 1. 39mW. The value of delay can be controlled by both fine-tuning and coarse-tuning. This time-delay cell can generate a delay of 14ns while it is able to reach a minimum delay of 6ns across a 100MHz bandwidth by using fine-tuning and coarse-tuning of the time-delay cell, as well. The proposed cell can be used in the beamforming, radars, and medical engineering. HSPICE simulations are performed based on a 0. 18µm standard CMOS technology.

This paper introduces four new resistorless circuits of first-order current-mode all-pass filter (CMAPF) based on dual-X current conveyor transconductance amplifier (DXCCTA). All the four circuits use a single DXCCTA and a capacitor for their realization. The main features of the proposed CMAPFs are: use of minimum active and passive components, resistorless realization, electronically adjustable pole frequency, easily cascadable, good sensitivity performance with respect to active and passive elements, low total harmonic distortion of output current (0.74%) and good operating frequency range (39.2 MHz). The non-ideal analysis of the proposed circuits has also been explored. Moreover, two applications of the proposed first-order CMAPF in terms of second order CMAPF and current-mode quadrature oscillator are also presented. HSPICE simulations have been carried out with 0.18 µm CMOS process parameters to validate the proposed circuits.

In this paper, a serial to parallel block for a 8-FFT processor in 0.13 um CMOS technology is presented. Because of more advantages of current mode circuits compared to voltage mode counterparts, in this design, it has been made effort to utilize these merits. Then, at first input voltage signal should be converted to current signal to be processed in current mode. After that, to parallel current signal the current mode sample and hold is employed. Two banks sample and hold are placed in proposed block diagram to synchronize 8 samples at the FFT input. The suggested serial to parallel block has the capability of producing the required samples at the same time with lower power consumption and higher speed. Also, because of applying the class AB current mirror the sample and hold is able to convey both peaks of the signal. It is shown that the power consumption of voltage to current converter is about 3 mW and each sample and hold draws 100 uA of 1.2 V power supply. Moreover, the whole block has approximately 5 mW power consumption. The 3dB frequency is placed at 125 MHz which impose limitation on sampling frequency of sample and hold circuit. In our application that is jamming mitigation in Global Positioning System (GPS) this limitation can be ignored because of low intermediate frequency (4MHz) of GPS.

In this paper a new structure for the MLF (Multi Loop Feedback) Gm-C group of filters is presented, granting the advantages of both current-mode and fully balanced topologies to the conventional structure of the group. The ability of the structure to perform even more transfer functions (Low pass and Band Pass) than other members of the group is proved. Methods of enabling the proposed structure to perform other popular transfer functions are also presented. The favorite feature of systematical generation of the structure facilitates its arrangement for any order. For practical comparison, a Butterworth 4th–order LP filter with a cut-off frequency of 10MHz is designed in three different structures viz; the proposed one, the single-ended current mode, and fully balanced voltage mode. Simulation results show that the PSRR+,PSRR-,CMRR, Noise, THD, DR, consumed power (P) and Figure of Merit (FOM) of the new structure compared to its voltage mode counterpart are improved at least by factors of 36643, 59841, 4.75, 76, 2, 2.45, 1.17 and 509500, respectively.Compared to single ended current-mode type they are improved by factors of 40, 73, not defined, 1.3, 7.8, 150, 0.68 and 1763000,respectively. Although the above mentioned comparison, due to both the similarity of the used technology and the completeness of the results, is the most equitable one for the most definite conclusion, to further widen the extent of the comparison, the proposed structure is also compared with some other works yet assumed as its closet counterparts. This latter comparison also proves the certain superiorities of the proposed structure such that its FOM is from 8500 to 4512740 times larger than those of others. Closer tracking of the input signal at pass-band and more attenuation at stop-band are also achieved by this structure. These results strongly support the theoretical suggestions. Most favorably the much higher PSRR of the new structure makes it an extremely suitable choice for Mix-Mode (System-On- a Chip, SOC/SOI) applications where power supplies (and analog blocks) suffer severely from digital noise.

In this paper a novel topology of CMIA based on FDCCII is proposed. Due to benefiting from current mode signal processing, unlike the most of the previously reported IAs, the proposed FDCCII based structure doesn't need well-matched resistors or active blocks to obtain high CMRR and inherently can improve CMRR, bandwidth, power consumption and it has better frequency performances. On the other side, unlike other current mode types of this group, using fully differential structure decreases the mismatch effect in electronic blocks. Both of these advantages significantly reduced the structure size and power consumption while improving bandwidth and CMRR and makes it an excellent and an unbeatable choice for integration. In the proposed circuit, CMRR as the most important property of IA has been greatly improved by using a current subtracting stage. The CMIA has been designed using 0.18 um CMOS Technology under ±1 V supply voltages and the performance of the CMIA has been verified using HSPICE software in transistor level. The CMIA has achieved voltage CMRR of 227.4 dB, voltage CMRR bandwidth of 8.98 KHz, differential voltage gain bandwidth of 9.08 MHz and output offset voltage of 2.23 uV and the IA’s power dissipation is only 348 uW

A new silicon ADC with digital error correction is introduced to reduce the linear error caused by inaccurate comparators and S / H offset. The operation of the new low voltage balanced current mode circuit in sampling and maintenance, signal amplification and current comparison function has been developed to detect how a silicon ADC silicon current mode with 1.5 V power supply works. Results are shown with Hspice to bring ADC at conversion rates of 10n / s and power losses of less than 2mW. In this simulation, SFDR is equal to 60 dB and ENOB is equal to 8, which are almost acceptable values.

One of the most widely used current mode circuits is the current conveyor circuit, so that after current mirrors, they are the most commonly used circuits in the analog field. The ability to process voltage and current at the same time, more bandwidth, gain more bandwidth and gain independence form bandwidth, are notable features of this circuit. In this article, we have designed a logarithm circuit with flow conveyors based on flow theory, so that while eliminating the defects of previous circuits, we can also have innovations in the design of a logarithm circuits. Presenting a new method for designing logarithmic circuit based on current mode, using current conveyors to design logarithmic circuit, using low power and voltage circuits, circuit design with temperature independent output and thus more stability are the results of this article. In this new method, relying on the mathematical relations that lead to the natural input logarithm, a new logarithm circuit is designed. Design of the new logarithm circuit is done in 180 microwatt technology, in the current mode. The current consumption of the circuit is about 5.96 µA, the power consumption is 2.98 µW, the gain is 69.7 dB and bandwidth is about 85 kHz. The correct operation of the designed circuit has been investigated by simulation in HSPICE and MATLAB software.

In this paper, a new structure of step-up dc-dc converter by using coupled inductor and active-clamped circuit is proposed. The proposed converter generates high voltage gain in comparison with the conventional dc-dc converters. Duo to using active-clamped circuit in the proposed topology the voltage stress on main switch is reduced. In addition the zero voltage switching (ZVS) in ON-state of main switch is obtained. In this paper the performance of the proposed structure is investigated in continues current mode (CCM) and discontinues current mode (DCM). Moreover, the voltage gain in CCM and DCM operations are calculated. To prove the correctness operation and also the given equations, the simulation results in PSCAD/EMTDC software are used.